July, 2011
www.us-tech.com
Page 59 Upping Performance with Through Silicon Vias (TSVs) Continued from page 52
processor below it. Together, the TSVs and MFIs carry the raw signals from the sensors to the CMOS for sig- nal conditioning, amplification, pro- cessing, actuation and other purposes.
Relieving Stresses MFIs are able to relieve thermo-
mechanical stresses very effectively because the curved beam is able to be deformed in the x, y and z dimen- sions and spring back to its original form when stress is removed. Currently the stand-off height between the two chips is 20 microns, but MFIs for other heights are in development. MFIs are fabricated by a multi-
step process that can be performed at the wafer level, or after the end of semiconductor back-end-of-the-line
Underfilling 3D Stacked PoP Devices
Continued from previous page
pensed and 0.2mm when only the bottom level interconnects were dis- pensed.
Wet-Out Area Underfill wet-out area is
greater the fewer the number of passes and if both interconnect lay- ers are being underfilled.
Results showed that the 2nd generation TSV PoP requires slightly more wet- out area than the 1st gen- eration PSvfBGA when using a single pass.
When laying out a board with a
PoP device the keep-out zone should not necessarily be symmetrical as the dispense side(s) require a wet-out area and the filleted sides of the package are primarily dependent on the height of the interconnect layer and contact angle of the material. This study showed that the wet-out area on a PoP was approximately 6- 10 times the fillet dimensions (3- 5mm vs 0.5mm). The fluid reservoir needs to reach as high as the second interconnect area, otherwise no underfill will flow into this area, the higher the reservoir the larger the wet-out area. The proximity to other compo-
nents determines the percentage of the total amount of material required to be dispensed in each pass. Dispensing less fluid in a pass enables the wet-out areas to be clos- er to the fillet dimensions because the fluid doesn’t spread as much and can flow under the component more quickly. Obviously, more passes take more time. It is advantageous from a cost and reliability standpoint to design the boards with an appropri- ate wet-out area for either single level interconnect or multiple level interconnect underfill. Contact: Nordson ASYMTEK,
2762 Loker Ave. West, Carlsbad, CA 92010 % 800-279-6835 or 760-431- 1919 fax: 760-431-2678 E-mail:
info@nordsonasymtek.com Web:
www.nordsonasymtek.com r
(BEOL) processes. The latter option permits MFIs to be fabricated on a CMOS chip. One potential problem in using
MFIs had been that the solder, which must be placed at the high point at the end of the beam, may flow away from the intended contact point dur- ing reflow. Dr. Bakir’s team solved this problem by placing a polymer ring at the tip of the beam. The poly- mer ring permits under-bump metal- lization with metals such a nickel. It also holds the solder in place during reflow. MFIs are not limited to con- necting a MEMS chip to a CMOS chip. Where thermomechanical stress is a concern, they can be used
to connect the CMOS chip to the sub- strate. They can also be used to fab- ricate a partly disposable MEMS package, where the MEMS chip, no longer useful because of its exposure to a substance being measured, can be removed and replaced by a new MEMS chip, thereby saving the pre- sumably more expensive CMOS IC. This is especially important when dealing with such devices as biosen- sors. It is also possible to use MFIs for temporary connection to bare die for high-speed testing before mount- ing of the IC. Will the combination of higher
speeds, better electrical performance, and better handling of thermome-
chanical stresses mean that TSVs and MFIs will pose a threat to convention- al wire-bonding for all products? Dr. Bakir thinks this is unlikely. Many products, he points out, perform very well using conventional wire-bonding. It is when the need for high intercon- nect density and heterogeneous inte- gration pushes designers into the realm of 3-D integration that TSVs and MFIs become necessary. Contact: Research News &
Publications Office, Georgia Institute of Technology, 75 Fifth Street, NW, Suite 314, Atlanta, GA 30308 % 404-894-6986 E-mail:
muhannad.bakir@
mirc.gatech.edu Web:
www.gatech.edu r
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