LED  inspection

Best Known Methods (BKMs)

Manual inspection techniques are inadequate for full wafer coverage and do not provide detection and classification results in a quantitative and repeatable manner. At best, manual inspection techniques might detect a rise in defectivity due to a major process excursion, but they will miss a transient increase in the severity of specific killer defects such as pits or hexagon bumps. Such minor excursions, subtle increases in killer defect densities, are virtually undetectable through manual inspection techniques, but can account for a substantial fraction of total yield loss.

Figure 5 shows the value of automated inspection for early detection of an epi reactor excursion of epi pits known to short the device p-n junction. The upper portion of the figure illustrates a minor excursion which goes undetected by manual inspection. A typical fab cycle through FWT is two to three weeks. Thus, for a manufacturer running at 20,000 wafer starts per month (WSPM) the feedback loop does not occur until the wafers reach electrical FWT. In the case of a two-week fab cycle, a minor excursion would expose 10,000 wafers to increased defect densities and increased yield loss. The lower portion of Figure 5 illustrates how automated inspection isolates the defect excursion.

Corrective actions quickly reduce defectivity levels to within process control limits. Fewer wafers are exposed to killer defects, reducing incremental yield loss. Early detection of excursions through automated inspection translates to millions of dollars in savings each year for LED chip makers. The cost of the MOCVD epitaxial layer is also an important contributor to overall device cost. MOCVD equipment accounts for about 65% of the capital cost of an LED fab (source: Bank of America Merrill Lynch Global Research, 2009). Maximizing the uptime and productivity of these systems is critical. Leading LED manufacturers use Candela defect data to implement SPC monitoring on each MOCVD reactor, thereby providing a rapid control loop should the defect density of a given reactor exceed process control limits.

Substrate and epi-layer defects

Common defects on sapphire substrates include particles, pits, scratches and CMP process stains. Substrate pits are known to cause GaN epi defects. Sapphire substrate stains are a root cause of localized areas of GaN epi roughness, where underlying high densities of atomic crystal dislocations can short device p-n junctions. Figure 6 illustrates the cause-and-effect of substrate stains on subsequent GaN-epi growth.

Automated inspection of incoming substrates verifies substrate quality. With clear pass/fail criteria,

April/May 2010 www.compoundsemiconductor.net 33

manufacturers can more readily set and enforce material quality specifications, raising both yield and overall device performance.

MOCVD processes produce a variety of GaN epi defects; common yield-impacting defects include hexagonal pits and bumps, crescents, circles, and other topographic defects. In addition to such device killers, GaN epi cracks are also known to be a significant reliability killer. As LEDs make their way into higher-end applications such as LCD backlighting, automotive, and general lighting, field reliability and LED performance longevity are of critical importance.

GaN epi cracks can be extremely problematic to LED makers as these defects cannot be screened at FWT or final probe test and only later result in field failures and expensive recalls.

Figures 7.a and 7.b illustrate Candela inspection images for GaN epi morphology and epi crack defects. These defects can be readily detected and classified in the output defect map.

Figure 5: The value of automated inspection for early detection of an epi reactor

excursion of epi pits

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