LED inspection
Epi defect correlation
KLA-Tencor’s inline inspection system is designed specifically for the defect inspection requirements of the LED industry. The optical design uses multi-channel detection technology to measure the scatter, reflectivity, phase shift, and topographic variations across the transparent substrate surface (Figure 2). Multiple measurements are made enabling production grade throughput and 100% surface coverage.
Figure 2: Candela design with multi- channel analysis to detect and classify a wide range of
mission-critical defects
variations. Epitaxial layer defects in particular can account for as much as 50% of the total wafer level yield budget. Industry leaders who use automated inspection to monitor defect densities within wafer, wafer-to-wafer, and batch-to- batch estimate that optimal inspection practices can reduce the yield impact of material defects and offer significantly higher yields.
Key inspection points across the front-end process include before and after cleaning and final preparation of substrates, and after deposition of the epitaxial layer (Figure 1). If a yield crash occurs, having data from multiple inspection points greatly simplifies the root cause analysis and helps prevent misguided process adjustments. There is no need to alter MOCVD process parameters when the underlying problem can be traced to incoming substrate quality.
After scanning, the analysis software extracts defects from the background signal, classifies them by defect type, and reports defect parameters and locations. For example, during inspection of polished sapphire substrates, the inspection recipe may include particles, scratches, pits, slurry residues and stains. Typical GaN-epitaxial layer defects include particles, scratches, micropits, microcracks, crescents, circles, hexagon bumps, and other topographic defects.
An analysis grid can be set to match the die dimensions, allowing correlations between individual defects and final wafer test results. For example, Figure 3 shows the influence of epi defects on device performance. In this study, the device die grid was overlaid on the Candela defect map and pass/fail criteria was set based on known killer defects (i.e. epi pits, crescents, hexagon bumps, and topography clusters). It is important to note that surface particles were omitted from the pass/fail criteria as surface particles are added and removed many times throughout processing.
After device fabrication, FWT electrical probe data was collected. Failed die were defined as those with a reverse leakage current greater than 1mA indicating a short of the device p-n junction. The corresponding yield map was overlaid with the Candela defect map to demonstrate the correlation between epi defects and LED device yield. Dies with known killer epi defects had a 52.1% failure rate (or kill ratio) at electrical testing, while dies without epi defects had only a 10.5% failure rate. Thus, dies with killer epi defects had a 5X greater probability of failure than those without defects.
Figure 3: Correlation of epi defects to LED device yield
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www.compoundsemiconductor.net April/May 2010
Figure 4 shows the bar graph of the yield loss for the samples in this study. From the correlation investigation, total yield loss can be partitioned into “epi defect induced yield loss” and “other sources of yield loss.” Other sources of yield loss include fabrication induced defects, particle and handling contamination, etc. The total yield loss after FWT for the three LED wafers analyzed was 15.3%, 17.5%, and 14.3% of which 6.0%, 7.2%, and 5.5%, respectively, could be attributed to epi defects. In this example, the epi defect induced yield loss represents roughly 40% of the total yield loss budget.
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