FC ASICs
• Fibre Channel has been designed from the start
to handle high volumes of Block I/O data at high
speed and low latency
• Typically all Fibre Channel Port functions are
implemented in hardware for speed
• A Fibre Channel chip uses approximately
500,000 gates
Fibre Channel
500K gates
Fibre Channel HBAs use ASICs to handle flow control and reliability:
Fibre Channel was designed to handle block-level storage on relatively
stable SANs.
Fibre Channel was designed for transport management services
implemented in silicon.
Fibre Channel ASICs are relatively simple, with about 500K gates.