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interview  EuroPIC


“We can see that the chip price may go down by a factor of more than ten. If the cost of packaging is not to become the bottleneck, it will have to go down too,which basically means cutting the cost of alignment using leading edge packaging technologies; ‘clip-it- together’ and ‘plug-and-play’ techniques.” Meint Smit, Technical University of Eindhoven


consortium that is very closely co-operating, which we have in Europe; and substantial supporting funding.


Q A


Where does the European foundry stand today?


DR: It’s at an R&D level. The University of Eindhoven is supporting the JePPIX operation, which runs an R&D generic line on its open facility.


What we are trying to do is to move that understanding and capability out into industry, where you can get all the good things like volume, reliability, throughput. To do this, EuroPIC is working with Oclaro in the UK and HHI (Heinrich Hertz Institute) in Berlin. Philips is also playing a role, although it is a little bit behind those to two foundries.


Although Oclaro’s technology is not advertised as large- scale photonic integrated circuits in quite the way Infinera’s technology is, it is every bit the equal of it. It can do very similar things, but Oclaro has chosen until now to apply it specifically to tunable lasers, modulators, and so on.


Q A


Q A


What are the benefits for Oclaro and HHI, the key foundries in the EuroPIC project?


DR: They are both fabs with a telecom base with a huge amount of highly sophisticated technology firmly directed in one narrow application area. They would both like to see their technological abilities more broadly deployed.


Tell me about the progress of EuroPIC?


DR: It started on 1st August last year, and it’s a relatively long cycle time to get the first generic line


set up. We have spent a year putting existing and new pieces together in the process phase, and we are just


34 www.compoundsemiconductor.net October 2010


We can see that the chip price may go down by a factor of more than ten. If the cost of packaging is not to become the bottleneck, it will have to go down too, which basically means cutting the cost of alignment using leading edge packaging technologies; ‘clip-it-together’ and ‘plug-and-play’ techniques.


about to start our first runs at the InP processing facilities. EuroPIC will aim to go through this cycle twice, in order to iron out difficulties.


MS: What has been achieved now is mainly coming from the JePPIX platform. This is research, but within two to three years we hope to bring this to an industrial level. We have selected ten different applications [see box “PIC applications” for details], and they will all be put on the two foundry lines. By the middle of next year we should have one set of wafers from each of the foundries, each wafer having a lot of quite different chips integrated on it.


Q A


Are the foundries continuing to refine their technology?


DR: Very much so. Although to be honest, EuroPIC is a very broad, SME-based program, and there’s


not that much space for developing a radically new semiconductor technology. The novelty in the program is largely to do with putting end-to-end process together, but there will be new technologies in packaging and software.


However, the platform is capable of considerable development in terms of the semiconductor technology that goes into it, because there are a lot of different InP alloys that you can use. There is the whole area of quantum dots and nanotechnology, which we could go into in the future.


Q A


Q A


What wavelengths will these PICs operate at?


MS: Initially the telecom C-band (around 1550 nm), but the platform is capable of extension.


Are there facilities to package these chips?


DR: Our packaging effort is rather small. There is a resource limitation – EuroPIC is a € 6 million


program. We have one partner who is beginning to look at the prospects of a generic packaging technology, CIP Technologies in the UK. We are also starting new programs, where packaging is a very large part of the activity.


MS: Our process is standardized on the interface electrically and optically, so that you can use the same package for a lot of different chips.


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