August, 2014
Shrinking ICs... Continued from page 59
products for improved logic density and bandwidth compared to planar 2D monolithic designs. The firm claims that field-programmable gate arrays (FPGAs) and transceiver mixed-signal die are integrated with more than 10,000 programmable interconnects within their packaged FPGA products through a silicon interposer as part of the SSI technology. As these 3D ICs scale down in
dimensions to line widths of 20nm and less, the package remains an essential part of protecting the circuitry from the outside world and, at the same time, providing reliable electrical intercon- nections to the circuitry within the package. For the most part, 3D IC cir- cuit designs are planned for use with conventional housings, including quad- flat-no-lead (QFN) packages, ball-grid- array (BGA) packages, and small-out- line-transistor (SOT) packages. But
www.us-
tech.com
Page 61
parts, such as an FPGA or MEMS layer within a 3D IC package. A num- ber of CAE software suppliers current- ly offer software design and simulation tools for 3D IC, including ANSYS (
www.ansys, which also offers a free white paper on 3D modeling), Cadence Design Systems (
www.cadence.com), and Mentor Graphics (
www.men -
tor.com), and some IC suppliers, such as Xilinx, also offer software design support, but any software tools must carry considerable capabilities to effec- tively aid in the design of a practical 3D IC. For example, power planning for a 2D IC can be difficult, to provide adequate power for all components within a planar IC. But for a 3D IC, power planning becomes even more difficult, since so many die on multiple stacks of a packaged IC must be con- sidered. Power distribution must be designed for the die, TSVs, and other portions of a multilayer 3D IC. In addition, effective CAE soft-
Interconnects for 3D packaging.
the complexity of 3D ICs often calls for more elaborate packaging solutions, including embedded-die approaches and fan-out wafer-level chip-scale packaging (WLCSP) approaches. Es - pec ially for the high pin counts that inevitably result from 3D IC designs, WLCSP housings are becoming more standardized and used with circuit designs requiring 100 or more package pins and even more complex 3D IC functions within, such as microelectro- mechanical-systems (MEMS) circuits. The use of TSVs within these packages enables the coexistence of different types of circuit functions on the differ- ent 3D IC layers.
Forging the Future A growing number of commercial
semiconductor foundries currently offer 3D IC fabrication capabilities, including Taiwan Semiconductor Man - u facturing Co. Ltd. (TSMC, www. - tsmc. com), GLOBALFOUN DRIES (www. g l o b a l f ound r i e s . c om) , TowerJazz (
www.towerjazz.com), and IBM Microelectronics (
www.ibm.com). Some of these foundries, such as TowerJazz, work closely with packag- ing specialists such as Interconnect Systems, Inc. (ISI,
www.isipkg.com) on providing advanced 3D packaging solutions for IC developers. In addi- tion, organizations have formed to pro- vide help for 3D IC designers. For example, the 3D IC Community (
www.3d-ics.com) supports the 3D IC design and development community with a centralized collection of news, blogs, and white papers on the topic, while the 3D-IC Alliance (www.3d-
ic.org) has been formed to support firms involved in the design and man- ufacture of 3D ICs. However, advancement of 3D ICs
will depend on two supporting func- tions:
computer-aided-engineering
(CAE) software tools with accurate models capable of simulating the per- formance and behavior of 3D ICs under a wide range of operating condi- tions, and test systems capable of pro- viding the measurement versatility needed to test a 3D IC as a whole and to also characterize its component
ware for 3D IC design should provide predictions not only of electrical per- formance at different operating tem- peratures, but of such parameters as thermal behavior and generation of electromagnetic interference (EMI). Thermal simulations alone can be challenging for a 3D IC with multiple layers and a possible mix of logic cells, digital and analog circuitry, power cir- cuitry, and RF/microwave circuitry.
Designing for Test Perhaps one of the most daunting
challenges that remains for developers of 3D ICs is the creation of effective and affordable test solutions for these 3D ICs. Current test probe technology, for example, is geared for much larger linewidths and features than found in many proposed 3D ICs. In addition, modern probe stations with hundreds of probe tips may require modification to thousands of probe tips to provide sufficient numbers of contact points for testing 3D ICs. Effective testing of 3D ICs will most likely require that 3D ICs and their packages be designed for testing, with interconnections within the IC optimized for test probe access and even package pins designed for access to desired parts of a 3D IC. Fortunately, major test-equip-
ment manufacturers are well aware of the challenges facing developers of 3D ICs. Current test solutions are limited, often providing only access to external package pins. Enhanced solutions are needed to perform integrity checks on the inter-die con- nections within the package. Some test software developers, such as Synopsys (
www.synopsys.com), have evaluated the needs of testing com- plex circuit designs, such as digital 3D ICs, and offer their DFTMAX™ test solution. It is a test tool that promises to reduce the costs of nanometer testing through dramatic reduction in test times even for multi-million-gate devices as well as significant reductions in test data. In the end, the complexity of
emerging packaged 3D IC devices will help to make life simpler for end users. With an electronics industry at work on fabs, design software, and test equipment to more cost-effec- tively produce complex 3D ICs, the end-user for the electronic products that these devices will serve, such as smart phones, tablet computers, and different types of sensors, will benefit with reliable products with greater functionality at lower costs. r
Page 1 |
Page 2 |
Page 3 |
Page 4 |
Page 5 |
Page 6 |
Page 7 |
Page 8 |
Page 9 |
Page 10 |
Page 11 |
Page 12 |
Page 13 |
Page 14 |
Page 15 |
Page 16 |
Page 17 |
Page 18 |
Page 19 |
Page 20 |
Page 21 |
Page 22 |
Page 23 |
Page 24 |
Page 25 |
Page 26 |
Page 27 |
Page 28 |
Page 29 |
Page 30 |
Page 31 |
Page 32 |
Page 33 |
Page 34 |
Page 35 |
Page 36 |
Page 37 |
Page 38 |
Page 39 |
Page 40 |
Page 41 |
Page 42 |
Page 43 |
Page 44 |
Page 45 |
Page 46 |
Page 47 |
Page 48 |
Page 49 |
Page 50 |
Page 51 |
Page 52 |
Page 53 |
Page 54 |
Page 55 |
Page 56 |
Page 57 |
Page 58 |
Page 59 |
Page 60 |
Page 61 |
Page 62 |
Page 63 |
Page 64 |
Page 65 |
Page 66 |
Page 67 |
Page 68 |
Page 69 |
Page 70 |
Page 71 |
Page 72 |
Page 73 |
Page 74 |
Page 75 |
Page 76 |
Page 77 |
Page 78 |
Page 79 |
Page 80 |
Page 81 |
Page 82 |
Page 83 |
Page 84