August, 2014
www.us-
tech.com Shrinking ICs Fit 3D Packaging By Jeffrey Paulownia D
esigning integrated circuits (ICs) in a verti- cal rather than a horizontal direction has long offered the promise of smaller chips
with highly integrated functionality and less power consumption in a single package compared to several devices in several packages. Yet, the design and manufacturing of three-dimensional (3D) ICs and their packages has never been easy. It poses many challenges, faced by device and package developers, by engineers assembling test solutions for 3D ICs, and even for the writers of electronic-design-automation (EDA) software for simulating the performance of these 3D ICs under different conditions. Still, with growing demands for numerous smaller ICs, such as microprocessors and sensors, the electronic industry is seeking ways to not only make these 3D ICs smaller and more reliable, but more cost effective as well. Of course, as markets for
portable electronic products, such as smart phones and tablet computers continue to expand, 3D ICs are also being targeted as solutions for achiev- ing smaller end-product sizes at lower operating power consumption and, hopefully, at lower manufacturing costs. As electronic products continue to boost capabilities in smaller hous- ings, the need increases for such devices as microprocessors with enhanced memory capabilities, and such devices can save space when mul- tiple microprocessor and memory cir- cuit layers can be “stacked” in a verti- cal direction, rather than spread out along a semiconductor wafer in a hori- zontal direction, in the manner of flip- chip devices. These 3D ICs are being planned
as replacements for multiple-function system-on-chip (SoC) devices which integrate multiple components and their functions onto a single silicon die which is then housed within a single package. An SoC, which may include a microprocessor, digital logic, memory, and additional components, may have hundreds of millions of gates and oper- ate at gigahertz rates. Fabricating these different functions on the same die can be challenging for any process. In addition, having analog and digital components in close proximity can lead to noise problems, and the costs of developing and testing these SoCs has been rising, leading to increasing inter- est in 3D ICs. One of the more critical features
in fabricating reliable 3D ICs is the interconnection between layers. Of course, not all 3D devices are fabri- cated from multiple layers on a single chip. In some cases, 3D devices are formed by means of system-in-pack- age (SiP) technology, where multiple ICs are stacked and interconnected within a single package. The vertical design approach is similar in both cases, with shorter interconnections required between device layers or separate ICs than compared to a hor- izontal approach. The shorter inter- connections resulting from the verti- cal design approach exhibit less par- asitic capacitance and require less power than the longer interconnec- tions of a horizontally designed, pla- nar approach. Heat buildup within densely
packaged 3D ICs is also a concern. Although the shorter interconnections in a 3D IC should amount to less power consumption and heat dissipation per interconnection than in a planar device design, the greater number of intercon- nections and higher density of those interconnections in a 3D IC package requires effective dissipation of heat from within the IC package. Silicon die
have generally been attached to SiP substrates by means of two-dimensional (2D) wire-bond or flip- chip. But 3D ICs typically incorporate a silicon inter- poser substrate to enable fine die-to-die interconnec-
tions; this substrate often includes through silicon viaholes (TSVs) to provide connections from upper metal layers to backside metal layers, to support heat flow. The TSVs are essentially copper via holes with diameters ranging from 1-30µm. The concept of a 3D IC is fairly simple, of posi-
Xilinx is now working on its second
generation of SoCs and 3D ICs, as well as its next-generation FPGAs.
tioning die to occupy vertical rather than horizontal space, but designing and realizing a 3D IC can be considerably more difficult than working with 2D ICs, perhaps the main reason that 3D IC technology is slow to see adoption in the industry. A number of IC suppliers have promoted their efforts and prod- ucts in 3D IC technologies, including Xilinx (www.xil-
inx.com) and Altera (
www.altera.com). Both offer products based on stacked die within compact hous- ings. In fact, Xilinx uses its stacked silicon intercon- nect (SSI) technology within its programmable 3D IC
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