IC packaging technology retrospective—part 7
been identified. These are the so-called
“vias first” and “vias last” methods. As the
names clearly imply, the differences are
predicated on when the interconnecting
vias are put into the silicon, before or after
the IC is created.
Vias-first structures are a product of
front end of line (FEOL) processing and
typically have smaller vias on the order
5-20 µm in diameter, resulting in aspect
ratios of from 3:1-10:1, depending on the
thickness of the wafer being processed. In
contrast, vias-last structures are typically
back end of line (BEOL) processed. The
two processes are compared in Figure 1.
The via diameters are generally greater,
20-50 µm, and the aspect ratios are
roughly the same; however the total range
reportedly runs the gamut from 1 µm
holes that are 10 µm deep to 90 µm holes
that more than 400 µm deep
2
. While the
use of lasers to form holes in the silicon
wafer has been described
3
, the via holes
are commonly generated in a plasma
using deep reactive-ion etching (DRIE),
a highly anisotropic etch process used
to create deep, straight-walled features
in silicon. After formation and before
plating, the vias must be lined with an
insulator to prevent poisoning of the
silicon when copper plated vias are formed.
!
One common approach is to oxidize the
!
exposed silicon walls to become silicon ! !
oxide or glass. While the high aspect ratio Figure 1. The two basic processes used for TSVs. The carrier used for the vias-last process serves until the assembly
plating is impressive given the feature sizes,
to the mating wafer is completed.
one must be mindful of the fact that the
CTE mismatch between silicon and copper
is significant (3ppm/˚C vs 18ppm/˚C),
interesting to see what comes next…. interconnection technologies. He was also
and fracture of the silicon is a real
formerly with Tessera Technologies, a global
possibility for larger diameter vias. Even
references leader in chip-scale packaging, where he was
so, the TSV process is looked to with great
1. US Pat No. 4394712, US Pat No. appointed to the first corporate fellowship for his
interest and will doubtless inspire more
4437109, and US Pat No. 4499655 innovations.
creative designs in the future.
2. http://www.semiconductor.net/
In summary, TSV technology is
article/205121-Through_Silicon_Vias_
an important new member of the IC
Ready_for_Volume_Manufacturing_.
packaging and interconnection family.
php#id3108112-0-a
It is also one that is blurring the once
3. Garrou, P. “Wafer Level 3D
bright lines between various elements
Integration: a Status Report”, 3D/
of the once highly structured electronic
SiP Advanced Packaging Symposium
interconnection hierarchy. There are
Proceedings, Research Triangle Park,
compelling arguments to be made for
NC May 9-10, 2007
TSV technologies, but there are also
risks. The future continues to unfold in
Verdant Electronics founder and president
interesting ways. The next stop in this
Joseph (Joe) Fjelstad has more than 35 years
journey is somewhere on the horizon,
of international experience in electronic
but its location is not yet clear. Those
interconnection and packaging technology in
involved in nanotechnology applied to
a variety of capacities from chemist to process
electronics are making measured streams
engineer and from international consultant
of announcements of their advances.
to CEO. Mr. Fjelstad is also a well known
One thing seems assured, and this is that
author writing on the subject of electronic
electronic packaging technology will not go
interconnection technologies. Prior to founding
away, and moreover it is likely to continue
Verdant, Mr. Fjelstad co-founded SiliconPipe
to increase in importance. It will be
a leader in the development of high speed
www.globalsmt.net Global SMT & Packaging – September 2009 – 5
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