Special packaging feature: Imbedded Component/Die Technology: Is it ready for mainstream design applications?
will see below examples of bumped die
and thin film passive devices that meet the
overall system design objective size weight
and power reduction. Integrating high den-
!
sity route out requires the use of imbed-
!
ding interposer designed bumped die into
Figure 6. Bumped die, wire bonded die, and thin Figure 7. Bumped die, wire bonded die, and thin film
a system card as seen in Figure 6.
film passives integrated on a high density interposer passives integrated on rigid flex substrate to eliminate
The ability to minimize connector
imbedded within a system card. failure opportunities due to connector systems.
systems requires the ability to use rigid flex
designs which allows one to fold up a sys-
tem level card as seen in Figure 7. Integrat-
ing the smallest form factor parts available
today is the design theme behind IC/DT
and its ability to create the smallest system
level electronic suite available.
Today’s designers now have a new
design suite which provides them with the
tools to design with SWAP as the objective
and insure the end result meets environ-
mental concerns, thermal management
issues, size, weight and less power because
they have the ability to model and simulate
IC/DT® design guidelines while the
individual PCB cards are being designed.
The future of integrating microelectronics
inside and alongside system level card de-
signs is now available today. Today we hear
about embedded passive and active devices
by leading edge companies in Europe and
Asia, and it is starting to filter into leading
Figure 4. Mixed-signal prototype to demonstrate IC/DT® packaging technology’s capabilities (left) and successful edge designs slowly. This is the infancy of a
test flight of prototype on SM-2 missile (right).
new design theory/technique which allows
one to design microelectronics inside a
electrically interconnect the devices (com- evaluation of the system in its intended
standard FR4 organic laminate structure.
ponent-to-component for point-to-point) weapon system to determine if it meets
IC/DT® is one of a few design techniques
and circuit (component-to-substrate for design specifications
10
.)
which is ready today to help shrink and
multi-point nodes). These flexible intercon-
make imbedding active and passive devices
nects are able to absorb the thermal and Future designs
a mainstream design guideline for future
mechanical stresses created when operating
system level electronic suites.
STI is currently designing four new layout
in harsh environments such as tempera-
concepts using IC/DT® that address
ture and vibration/shock thus increasing
conclusion
SWAP—size weight and power reduction
robustness of the assembly. Elimination
The testing of the two test vehicles has
techniques that are suited for hi-reliability
of secondary packaging, which facilitates
demonstrated that Imbedded Component/
requirements. These designs utilize a
bonding from component-to-component,
Die Technology (IC/DT®) is a robust
number of different components and die
decreases the number of failure opportuni-
that meet the re-
ties in the system thus increasing overall
quirement for the
reliability.
smallest form and
The IC/DT® prototype was analyzed
fit factor devices
and tested by SM-2 prime contractor Ray-
available today.
theon Missile Systems, which approved the
The idea is that
prototype as flight hardware. This included
one must utilize
finite element analysis (FEA) design model-
ing and prototype qualification testing per
the smallest form
standard legacy performance requirements
and fit factor de-
and overstress test requirements (extended
vices available in
temperature, humidity, vibration testing).
the market place
In October 2007, the IC/DT® prototype’s
today without
performance and robustness were demon-
their secondary
strated through a successful SM-2 flight
packaging to be
test, thus advancing the IC/DT technol-
able to design the
ogy to TRL 8 status (TRL 8 Definition:
smallest form and
Technology has been proven to work in its
fit factor circuit
final form and under expected conditions. card assemblies.
Examples include developmental test and To that end, you Figure 5. Wires bonded to electrically interconnect components on the prototype.
32 – Global SMT & Packaging – September 2009
www.globalsmt.net
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