Special packaging feature: Imbedded Component/Die Technology: Is it ready for mainstream design applications?
a single high-density module. ics product.
!
2/"!/34'+5!
Miniaturization is achieved fundamen- IC/DT® im-
&366!
tally due to the elimination of external proves long-term "#$%!&'()!
component packaging. IC/DT® utilizes signal reliability
*$+)(,#$$),+!
unpackaged components, known as bare by eliminating un-
die, for design with the smallest form and necessary failure *-.)%%)%!
fit factor available. Component geometries opportunities and
/#-0#$)$+1!
can be reduced up to 85% through the utilizing reliable
removal of external lead frames, package electrical intercon-
substrates, and overmold encapsulants. nects. All first
These die are then imbedded in openings/ level component
cut-outs of the PCB, commonly referred packaging is elimi-
!
to as cavities (Figure 1). Imbedding die in nated. This elimi- Figure 1. Active and passive components are imbedded in a cavity on a laminate
cavities in the substrate facilitates Z-inte- nates two to four
substrate.
gration through imbedding die on tiers, or possible modes of
exposed layers, within the substrate. electrical failure
With the available real estate on the associated with
PCB provided by reduced component foot- component-level
prints, additional systems or capabilities packaging. Due to
can be added to an electronics assembly. the removal of ex-
System capabilities can be increased ternal packaging,
through the integration of additional electrical parasit-
features and functionality and/or redun- ics and thermal
dant system within the same envelope. For resistance are
example, processing architectures, such reduced improv-
as those implemented in field program- ing overall system Figure 2. High-resolution images of daisy-chain die imbedded in the central cavity:
mable gate arrays (FPGAs), may be easily performance as
upper left die (left) and lower left die (right).
scaled to increase the number of process- desired in high
ing elements (increased capability and speed, high I/O
Test vehicle 1
system functionality) within the same PCB systems such as those found in missile
A test vehicle was designed to evaluate the
envelope due to component-level miniatur- defense systems.
ization. Conventionally, a high power CCA
effectiveness of assembly materials in harsh
Elimination of secondary packaging would dissipate heat through convection
environments when imbedding bare die
materials plays a significant role in the or radiation from the component and
(silicon die) in organic laminate substrates.
overall weight reduction achieved through substrate surfaces, often including package-
The test vehicle consisted of multiple
imbedding unpackaged die. Interconnect level heat sinks or cooling fans. However,
imbedded die (Figure 2) wired to inner
materials that physically and electrically advanced handheld applications inhibit
layer tiers for monitoring fluctuations in
connect the integrated circuits (ICs) die to the use of these passive and active cooling
resistance during/after environmental
the circuitry are eliminated. In addition devices. Therefore, IC/DT® provides a
testing. The imbedded test die consisted
to the reduction in component packaging solution through relying on passive cooling
of daisy-chain components with peripheral
mass, there is also a reduction in the mass via conduction to a single, central cooling
bond pads for interconnecting to a test
related to the electrical interconnect mate- core to remove heat from high power substrate. Test patterns on the high tem-
rial. A significant mass savings is achieved devices and to evenly distribute the ther- perature FR4 (HT-FR4) laminate substrate
by using wire bonds rather than solder be- mal energy along the interface. Through enabled in-situ resistance monitoring of
cause of the decreased volume of material creative thermal management, die junc- the assembly during testing. A conformal
per connection, as well as the lower density tion temperatures (T
J
) are reduced which coating, encapsulant, and lid were used
of typical bonding wire alloys compared to increases the performance and longevity
(Figure 3) to protect the imbedded die from
solder. of the electronic components and further
physical damage (handling/transportation)
Reliability of the end product is increases system-level reliability
3
.
and the environments (ionic contamina-
improved not only by a reduction in
tion, moisture ingression, and vibration
interconnect material mass (translates to Technology prototypes
dampening).
less applied force [F=ma] under load), but STI has recently completed testing of two
also through the increased flexibility of prototype vehicles to serve as a technology
Test Coupon Parameters
the electrical attachment. Through the
demonstration of the design guidelines,
• Substrate: 4.0 x 6.0 inch HT-
use of wire bonding technology as the
materials, and manufacturing processes
FR4, laminate PCB, three tiers
electrical interconnect process, very flexible
used to imbed passive and active devices in
• Imbedded Core: copper core,
light-weight interconnects are created. This
laminate substrates
12
. Environmental stress
Ni/Au plating
flexibility is exploited during operation
testing was conducted on these prototypes
• Die: 0.248 x 0.240 inch silicon
in demanding thermal and mechanical
to evaluate the robustness of imbedded
die, daisy-chain design, periph-
environments such as high temperature,
bare die in an organic laminate substrate
vibration, and/or mechanical shock. In
eral wire bond pads
in conventional military and aerospace
contrast to a soldered connection, which
• Die Attach: compliant epoxy,
environments (harsh environments).
localizes the applied stress, the IC/DT®
thermally conductive, electri-
concept distributes the applied stress pro-
cally insulative
ducing a more robust and rugged electron-
• Interconnect: Al/1%Si wire
www.globalsmt.net Global SMT & Packaging – September 2009 – 29
Page 1 |
Page 2 |
Page 3 |
Page 4 |
Page 5 |
Page 6 |
Page 7 |
Page 8 |
Page 9 |
Page 10 |
Page 11 |
Page 12 |
Page 13 |
Page 14 |
Page 15 |
Page 16 |
Page 17 |
Page 18 |
Page 19 |
Page 20 |
Page 21 |
Page 22 |
Page 23 |
Page 24 |
Page 25 |
Page 26 |
Page 27 |
Page 28 |
Page 29 |
Page 30 |
Page 31 |
Page 32 |
Page 33 |
Page 34 |
Page 35 |
Page 36 |
Page 37 |
Page 38 |
Page 39 |
Page 40 |
Page 41 |
Page 42 |
Page 43 |
Page 44 |
Page 45 |
Page 46 |
Page 47 |
Page 48 |
Page 49 |
Page 50 |
Page 51 |
Page 52 |
Page 53 |
Page 54 |
Page 55 |
Page 56