Title
IC packaging technology retrospective—part 7
Joe Fjelstad
IC packaging technology
retrospective—part 7
Through silicon via (TSV) technology—another ‘More than
Moore’ solution
The previous part of this series left off transistor density per unit area by turning chip’s power consumption requirements.
with a discussion of 3-D package assembly attention to the third dimension. Through silicon via technology also serves
at both the chip and package level. There are, at present count, several the purpose of allowing the designer to
However, the discussion was limited to different prospective drivers for the integrate mixed technologies in the form of
the most common extant technologies for development of interconnection solutions different functional layers of a TSV silicon
interconnection, which presently includes based on TSV technology. First, there is stack assembly, where one might include
wire bonding and flip chip. There is a the small size form factor, which allows optimized analog and digital, RF circuits,
more recent interconnection technology the developer to increase circuit density inductors, memory devices, logic devices,
that is of high interest at this time. It is and achieve the highest electronic circuit imagers and sensors (e.g., MEMS devices)
known by the term through silicon via to volume ratio. Regular readers will all into a common assembly. Finally and
technology, or TSV. Like many of the other recall that the term “volumetric system not insignificantly, there is cost. While
technologies discussed in this series, TSV miniaturization and interconnection,” or there is some distance still to travel,
technology, as a many pundits
concept, is not believe that
all that new. in the future,
For example, in
“Like many of the other technologies
especially if yields
the early 1980s are good, 3D
the creation of
discussed in this series, TSV technology, as
integration will
feed-through prove cheaper
conductors
for use in
a concept, is not all that new. ”
than relentlessly
shrinking
the assembly transistors and
of stackable the pursuit of
silicon-on-sapphire wafers was described by VSMI, has been applied to describe this system on chip (SOC) developments. Logic
researchers at General Electric
1
and many objective in a general manner. A second seems to readily agree with the premise but
of today’s inkjet print head technology driver is the desire to increase electrical there is, as was just stated, a long way to go
providers rely on through silicon via performance (circuit speed) by shortening to prove the assertion beyond doubt.
technology to create their own special electronic interconnection path length. As for the technology, there are several
brand of magic and have done so for When frequencies increase, so also does different implementations that have been
many years. Moreover, MEMS developers their susceptibility to parasitic effects, explored or proposed. Some involve whole
have pioneered many of the processes especially if the circuits are dense and wafers stacked one atop another in a
that now find their way into TSV. That circuit paths are long; thus TSVs can method that seems best suited to memory.
said, there have been some significant help to improve electrical performance Others involve the placement of chips
developments in recent years and TVS by reducing electrical parasitic effects due on top of wafers or atop other chips. The
technology is being hailed as another to RC delays in high frequency or high latter method is one that is best suited to
member of the “More than Moore” family speed applications such as RF and fast the integration objectives just described
of interconnection solutions that combine memory applications. The use of TSVs above. As for TSV technology basics, there
to push out the edges of the envelope of can also help to significantly reduce the IC are two fundamental methods that have
4 – Global SMT & Packaging – September 2009 www.globalsmt.net
Page 1  |  Page 2  |  Page 3  |  Page 4  |  Page 5  |  Page 6  |  Page 7  |  Page 8  |  Page 9  |  Page 10  |  Page 11  |  Page 12  |  Page 13  |  Page 14  |  Page 15  |  Page 16  |  Page 17  |  Page 18  |  Page 19  |  Page 20  |  Page 21  |  Page 22  |  Page 23  |  Page 24  |  Page 25  |  Page 26  |  Page 27  |  Page 28  |  Page 29  |  Page 30  |  Page 31  |  Page 32  |  Page 33  |  Page 34  |  Page 35  |  Page 36  |  Page 37  |  Page 38  |  Page 39  |  Page 40  |  Page 41  |  Page 42  |  Page 43  |  Page 44  |  Page 45  |  Page 46  |  Page 47  |  Page 48  |  Page 49  |  Page 50  |  Page 51  |  Page 52  |  Page 53  |  Page 54  |  Page 55  |  Page 56