Special packaging feature: IC packaging and interconnection technologies’ 4th dimension challenge

Special packaging feature:
IC packaging and
interconnection technologies’
4th dimension challenge
by Joseph Fjelstad
Over the course of the last five or six be weighed through when making the
years there has been an explosion of decision to use any of these approaches.
innovation in the realm of IC packaging. Perhaps one of the greatest collective
Most of the attention has been focused advantages of the 3D is the ability to
on methods and structures that allow for allow the system designer to mix and
ever greater density and the pursuit of match technologies that cannot be viably
stacked packaging concepts or, as they produced on one wafer. Analog and digital,
have come to be known collectively, 3D silicon and gallium arsenide: however one
packaging. The current third dimension wishes to parse it, the doors are opened by
paradigm was cleverly identified as the these various 3D solutions.
‘More than Moore’ alternative to ‘More With all of the attention given to
of Moore.’ The latter was an obvious 3D packaging, there still is another
reference to ‘Moore’s Law,’ which predicted dimension of the universe that needs to
the doubling of transistors on ICs every be factored into the equation and that is
18-24 months based on a reduction in the dimension of time, the so-called 4th
feature sizes predicated on constant dimension. Time is fascinating. So far as
Tessera’s µPILR™ PoP interconnect solution.
improvement in semiconductor processing we know, it is infinite in quantity and thus
methods, most importantly in the area could be seen as a cheap commodity, but in
of lithography. With semiconductor At the present time, 3D IC packaging business as in life, experience teaches that
technology once again approaching the technologies can be broken into three there is perhaps nothing more valuable
predicted boundary of its limits (it has general categories. First is the stacked- than time. Development time, time to
been predicted before, more than once), chip-in-package solutions offered by market, shipping time, time management,
many scientists and lead time, overtime,
engineers believe product lifetime….
that this time both Time is a factor in
the physical limits
“So far as we know [time] is infinite in quantity
nearly every business
and the limits of analysis and decision
physics are for
and thus could be seen as a cheap commodity.”
(and probably should
real. That said, be in our personal
experience says lives as well). With
that there is need respect to electronics
to leave open the door to an unforeseen major package developers Amkor, STATS design, IC packaging and interconnection,
breakthrough that could push the limits ChipPAC and others. These solutions the 4th dimension has another important
out a bit further, but there is likely going include both wire bonded and flip chip role and challenge, and that is to decrease
to be a point of diminishing returns. A interconnections as well as stacked chip time of flight for electronic signals. The
number of semiconductor manufacturers packages that are combinations of the operational speed of an electronic system
have already acknowledged this by turning two. The second category is the stacked is directly related to its interconnection
back and using higher yielding, earlier IC package category, which includes architecture. This has been covered in
generation technologies rather than the the various lead frame and ball stack this column before on a number of
leading edge, in order to improve margins technologies as well as the newer µPILR™ occasions , describing how direct chip to
and competitiveness. What they are from pioneering CSP developer Tessera. chip interconnection by means of a 3rd
concluding is that it makes more sense The third category is a developing one that dimension ‘super highway’ could increase
to solve transistor density challenges with involves stacking of wafers using through system performance.
finesse in IC packaging rather than brute silicon vias to allow direct interconnection Super computer pioneer Seymour Cray
force lithographic gains. As a result, IC between IC circuits. This latter approach knew system architecture was critical. It
packaging is now becoming the solution of makes sense, but it is not trivial as there was the cornerstone of his designs. More
choice in many design situations. are many considerations that need to recently, Andreas (Andy) Bechtolsheim,
34 – Global SMT & Packaging – September 2009 www.globalsmt.net
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