Vendor viewpoint
Figure 1: Typical dome PSS feature
GaN Etching
The chemical stability and high bond strength, it’s melting point, (25000C) and bond energy (8.9eV/atom), associated with GaN also make it highly resistant to wet etching in either acid or alkali based etchants. To date, the lack of a suitable wet etch for processing has resulted in much interest in developing dry etch processes suitable for HBLED production, with the same necessity to etch large numbers of wafers in a single batch. Plasma etch batch sizes have increased from 4 x 2” wafers in the late nineties up to 55 x 2” or 3 x 8” today, the question now is how big can the batch size go before it becomes unattractive. This is mitigated as the wafer sizes migrate upwards from 2” to 4” and then 6”. The main areas of GaN etching are:
Shallow contact etch
When etching down to a contact layer it is vital that minimal plasma damage is caused to the semiconductor otherwise an increase in contact resistance can occur. Careful optimisation of the etch process is required to maximise throughput while maintaining device performance. Smooth surfaces typically indicate a high quality etch as shown in Figure 2.
Figure 2: Shallow GaN etch for device
contact PR remains on the sample
the heat load on the sample therefore, to use PR as a mask and maintain a high etch rate, it is necessary to actively cool the wafer sample.
The silicon industry is accustomed to clamping single wafers to a temperature-controlled table, and introducing a heat transfer medium, normally helium, between the table and the wafer. ‘Helium backside cooling’ has become the standard method for single wafer temperature control. HBLED manufacturing currently uses batches of smaller substrates, passed into the etch tool on a carrier plate. For Patterned Sapphire Substrate (PSS) etching, HBLED devices are still mostly manufactured on 2” or 4” wafers, therefore to significantly reduce costs it is desirable to process as many wafers in one run as possible.
Etching large numbers of wafers with a PR mask requires good temperature control of each wafer, and this requires an understanding of how to transfer the heat from the plasma away from the samples to the cooled electrode. Helium backside cooling is the key, and understanding how to enable this for every wafer ensures success. Batch sizes for this technique are up to 20 x 2” with etch rates between 50nm/min and 100nm/min depending on the PR mask and PSS shape requirements.
44
www.compoundsemiconductor.net November/December 2011
Unoptimised etch processing can lead to threading dislocations in the GaN etching preferentially leading to a pitted surface and increase in contact resistance. Again PR is the mask of choice for this step as it is the most simple process regime. The use of PR leads to a reduction in powers used due to the temperature limitations with typical batch etch rates upto 150nm/min reported.
Deep isolation etch
Etch rate is key to this process as depths of up to 7µm can be required. The function of this step is to etch down the underlying sapphire substrate in between the active devices. As sapphire is electrically non- conducting this isolates the devices before physical separation. The key challenges with this etch step are heat removal if a PR mask is used, as high etch rates
Figure 3: Deep,high aspect ratio GaN etch SEM image from Philip Shields, University of Bath
Page 1 |
Page 2 |
Page 3 |
Page 4 |
Page 5 |
Page 6 |
Page 7 |
Page 8 |
Page 9 |
Page 10 |
Page 11 |
Page 12 |
Page 13 |
Page 14 |
Page 15 |
Page 16 |
Page 17 |
Page 18 |
Page 19 |
Page 20 |
Page 21 |
Page 22 |
Page 23 |
Page 24 |
Page 25 |
Page 26 |
Page 27 |
Page 28 |
Page 29 |
Page 30 |
Page 31 |
Page 32 |
Page 33 |
Page 34 |
Page 35 |
Page 36 |
Page 37 |
Page 38 |
Page 39 |
Page 40 |
Page 41 |
Page 42 |
Page 43 |
Page 44 |
Page 45 |
Page 46 |
Page 47 |
Page 48 |
Page 49 |
Page 50 |
Page 51 |
Page 52 |
Page 53 |
Page 54 |
Page 55 |
Page 56 |
Page 57 |
Page 58 |
Page 59 |
Page 60 |
Page 61 |
Page 62 |
Page 63 |
Page 64 |
Page 65 |
Page 66 |
Page 67 |
Page 68 |
Page 69 |
Page 70 |
Page 71 |
Page 72 |
Page 73 |
Page 74 |
Page 75 |
Page 76 |
Page 77 |
Page 78 |
Page 79 |
Page 80 |
Page 81 |
Page 82 |
Page 83 |
Page 84 |
Page 85 |
Page 86 |
Page 87 |
Page 88 |
Page 89 |
Page 90 |
Page 91 |
Page 92 |
Page 93 |
Page 94 |
Page 95 |
Page 96 |
Page 97 |
Page 98 |
Page 99 |
Page 100 |
Page 101 |
Page 102 |
Page 103 |
Page 104 |
Page 105 |
Page 106 |
Page 107 |
Page 108 |
Page 109 |
Page 110 |
Page 111 |
Page 112 |
Page 113 |
Page 114 |
Page 115 |
Page 116 |
Page 117 |
Page 118 |
Page 119 |
Page 120 |
Page 121 |
Page 122 |
Page 123 |
Page 124 |
Page 125 |
Page 126 |
Page 127 |
Page 128 |
Page 129 |
Page 130 |
Page 131 |
Page 132 |
Page 133 |
Page 134 |
Page 135 |
Page 136 |
Page 137 |
Page 138 |
Page 139 |
Page 140 |
Page 141 |
Page 142 |
Page 143 |
Page 144 |
Page 145 |
Page 146 |
Page 147 |
Page 148 |
Page 149 |
Page 150 |
Page 151 |
Page 152 |
Page 153 |
Page 154 |
Page 155 |
Page 156 |
Page 157 |
Page 158 |
Page 159 |
Page 160 |
Page 161 |
Page 162 |
Page 163 |
Page 164 |
Page 165 |
Page 166 |
Page 167 |
Page 168 |
Page 169 |
Page 170 |
Page 171 |
Page 172 |
Page 173 |
Page 174 |
Page 175 |
Page 176 |
Page 177 |
Page 178 |
Page 179 |
Page 180 |
Page 181 |
Page 182 |
Page 183 |
Page 184 |
Page 185 |
Page 186 |
Page 187 |
Page 188 |
Page 189 |
Page 190 |
Page 191 |
Page 192 |
Page 193 |
Page 194 |
Page 195 |
Page 196 |
Page 197 |
Page 198 |
Page 199 |
Page 200 |
Page 201 |
Page 202 |
Page 203 |
Page 204 |
Page 205 |
Page 206 |
Page 207 |
Page 208 |
Page 209 |
Page 210 |
Page 211 |
Page 212 |
Page 213 |
Page 214 |
Page 215 |
Page 216 |
Page 217 |
Page 218 |
Page 219 |
Page 220 |
Page 221 |
Page 222 |
Page 223 |
Page 224 |
Page 225 |
Page 226 |
Page 227 |
Page 228 |
Page 229 |
Page 230 |
Page 231 |
Page 232 |
Page 233 |
Page 234 |
Page 235 |
Page 236 |
Page 237 |
Page 238 |
Page 239 |
Page 240 |
Page 241 |
Page 242 |
Page 243 |
Page 244 |
Page 245 |
Page 246 |
Page 247 |
Page 248 |
Page 249 |
Page 250 |
Page 251 |
Page 252 |
Page 253 |
Page 254 |
Page 255