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ther code plugins would not disrupt the basic architecture of the system.
Further Standards The first of the plugins that
would add functionality to ProVision was the facility to test AC-coupled LVDS signals, controlled by logic that was compliant to the newest IEEE std. 1149.6. Dot 6 introduced new instructions in the BSDL model and new logic structures into the compliant parts. Two new instruc- tions can be used to fire a high-speed pulse (EXTEST_PULSE) or a series of pulses (EXTEST_TRAIN) across the network being tested. To com- plete the picture it is necessary to add a complementary receiver circuit that can reconstruct the pulse signal after it has degraded during its tran- sition through the AC-coupling. As the migration from wide par-
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allel busses to high-speed serial con- tinues apace, we can expect to see more devices supporting the dot 6 test meth od. Even some new mem - ories, such as Micron’s hybrid memo- ry cube, are already equip - ped with dot 6 test fea- tures, as are many bus bridges from PLX. The next standard to
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be ratified was, unsurpris- ingly, IEEE 1149.7, some- times known as CJTAG (compact JTAG or dot 7). However, there is a great deal more to this standard than its title suggests. Originally developed by IC vendors, including Texas Instruments (TI), dot 7 is an amalgam of a number of confused features wrapped under one standard. As yet, only a few, mainly TI developed devices, are supporting dot 7. This may be due to the fact that other “compact” debug interfaces already exist; take SWD for example, and that subsequent standards have also addressed the power management and segmenta- tion issues to some extent. As always, time will tell if dot 7 flourish- es or fails — as can happen when a standard is defined from a single- minded purpose. The next significant update to
standards came in 2013 with a siz- able addendum to IEEE 1149.1 — IEEE 1149.1 (2013). This standard came about during a period of intense activity around 2010, with two separate groups proposing simi- lar updates to the existing 1149.1 standard, which was by then 20 years old. The drive behind the changes was to standardize such fea- tures as initialization protocols, indi- vidual device ID codes and power management scenarios.
JTAG Developments Far from making JTAG/bound-
ary-scan an exclusive system for pro- duction test engineers or debug access, several new systems have emerged that promote JTAG/bound- ary-scan testing to hardware devel- opment engineers. Aware of the fact that short-run prototype systems are likely to be more prone to manufac- turing faults than those built on an established, process-proven produc- tion line, boundary-scan has been promoted to designers as a tool for board bring-up and validation. One
of the systems that entered this hardware validation market in 2009 was JTAGLive, which included a free “downloadable” point-to-point inter- connect system called Buzz, and received thousands of downloads upon introduction. For the first time, designers
could use a free tool to conduct inter- connect tests using equipment that they already had. What’s more, users with an appetite for more capability could bolt on options such as a pow- erful Python-based scripting system and even core emulation modules to enable what is sometimes referred to as a “processor control test”. In 2011, a completely new tech-
nique for harnessing the power of JTAG was introduced that allowed it to be applied to designs without prior knowledge of the interconnect data. Known as AutoBuzz, a user could simply connect a compatible con- troller to the TAP of the design, which would detect the number of parts in each scan chain, plus their manufacturer code. After assigning BSDL models to the detected parts the user could set AutoBuzz to scan
JTAG has developed a block translator
code that offers generic access to embedded IP connection busses.
connections on a known good board. By toggling each drive pin in turn and looking for activity on input pins, a basic “connectivity signature” is produced that shows the connected boundary-scan drive and sense cells. Using a compare mode the system can then assess a faulty board and highlight any disparities in the sig- nature. Asynchronous drives that can interfere with the process can be masked for consistent results.
Looking Toward the Future The argument for the continued
development of standards is clear. Chiefly, these are to keep the tech- nology relevant to today’s designs, to ease the task of tool vendors who rely on standard techniques to achieve maximum levels of automation in application generation, and to expand the market potential of a given methodology. We can expect expansion of the
features for enabling JTAG to go in two different directions. First, there will be more embedded testing at the device level, and extended infrastruc- tures for system-level access and test. Following the demise of the 1149.5 MTM bus several years ago, the latter requirement now appears to be a one-horse race under the direction of the SJTAG committee. However, it is a slow process
and though the SJTAG group was formed 10 years ago, there have been difficulties in nailing down a precise definition for their project. The impli- cation may be that the industry has worked satisfactorily with the cur- rent levels of solutions — mainly
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