June, 2016
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JTAG and Boundary-Scan Past, Present and Future
By Peter van den Eijnden, Managing Director, JTAG Technologies
prompted a group of production test engineers to consider the impact of these parts on the testing of their assemblies. They called themselves the Joint European Test Action Group (JETAG) and were made up of repre- sentatives from Philips, BT, GEC, Siemans, Plessey, and others. In most cases up to the mid-1980s, tests were accomplished by in-circuit testers (ICTs) for individual component and PCB testing, or function testers that mimic the environment of the UUT to send and receive stimulus and response signals. With advent of SMT and higher levels of integration, test access for ICTs was greatly dimin- ished. In addition, due to the higher integration levels, functional test became a more arduous process.
A
JTAG’s Beginnings It was at this point that the
JETAG committee started to think about a mechanism for embedding test capabilities into the devices themselves. Before long, the commit- tee gained more members from “The New World” and the group’s name became the simpler JTAG that we know today. The fruits of their labor, “The Test Access Port and Boundary- Scan Architecture”, described how a serial scan register could access digi- tal signal pins of a device to either capture an input signal or propagate an output signal through the pin of the part, while isolating the part’s regular function. A number of support registers, including the instruction register and bypass register, and a state-machine (TAP controller) com- pleted the picture. In 1990, the sys- tem was proposed to the IEEE com- puter standards authority, and a bal- lot approved the IEEE 1149.1 stan- dard. A few years later, IEEE std. 1149.1b, an addendum, described a precise syntax for a device modeling language, BSDL, which was based broadly on VHDL. With the ability to describe an
individual device’s boundary-scan capability in BSDL, along with CAD data that described the interconnec- tions between parts in a design, it became possible to develop automat- ic test program generators that could devise a test to detect 100 percent of shorts or opens in the interconnec- tions on a device supporting JTAG. One of the first of these, by Philips Test and Measurement, which later became JTAG Technologies, was known as BTPG_I (Boundary-Scan Test Program Generator for Inter - connects). This set the stage for a 25- year development program of im - proving JTAG-oriented test products built upon standards. Engineers working on the tools
to support IEEE std. 1149.1 (JTAG and boundary-scan) realized that the access provided by the principle boundary-scan register (BSR) could also be used to stimulate standard parts in the same way that ICT I/O pins had in the past. Soon they had added the capability to stimulate memory write and reads from the JTAG part to memories such as SRAMs, FIFOs and DRAMs. By
lmost 30 years ago, the change in device packaging from through-hole to surface-mount
applying a carefully devised, compact set of test vectors, a test could be made to detect opens and shorts on the signals to and from the memory cluster. An advanced diagnostics model gave a pin-level description of the fault.
Programmable Logic and Fault Coverage
The next major development in Timeline of JTAG test development.
harnessing JTAG for production was the introduction of programmable logic parts that used JTAG not only
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