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Page 55 JTAG and Boundary-Scan — Past, Present and Future Continued from page 53


to access boundary-scan test features, but also to scan data into configuration registers so that they could be programmed in-system. Among the first vendors to offer this feature were Intel (before they sold their PLD lines to Altera), Xilinx and Altera. It could be argued that the ability to program


parts in-system so excited the production communi- ty that an extension to the tools to allow program- ming other parts, such as flash and serial PROMs, became inevitable. Indeed, by 1996 the first auto- mated flash programming application generator, driven by JTAG, was introduced along with com- panion high-speed controller hardware — the latter being necessary to provide a reasonable rapid throughput for images that were already approach- ing a few megabytes at the time. JTAG Tech - nologies further improved the throughput of these systems by adding the extra control line, AutoWrite™, to pulse the WE_ of the target flash and save two complete shift cycles, as opposed to pulsing WE_ by using the boundary register. AutoWrite is now a standard feature of the DataBlaster family of high-per- formance controllers. By 1999, the developments of


the analog variant of the IEEE stan- dard (IEEE std. 1149.4) was com- plete, and a number of products ten- tatively reached the market. The standard itself was simple enough. Alongside the current 1149.1 cells, or digital boundary modules (DBMs), there would be analog boundary modules (ABMs). The ABMs incorpo- rated a switching network connected between the pin and the core circuit- ry. This allowed the analog pin to be put into the core disconnect state, which isolates it from the core, and also allows it to be connected to either an external signal connected to that pin, an internal DC voltage, or the internal analog test bus. The internal analog test bus consisted of two lines, and when added to the con- ventional dot 1 TAP lines, made up the Analog Test Access Port (ATAP).


The Turn of the Millennium A new aspect of boundary-scan


technology that emerged around the same time as dot 4 was a system that could predict and evaluate fault cover- age on a board. Initially known as Boundary-Scan Fault Coverage Exam - iner (BFCE), the system could read netlist data, BSDL device models and other active device model data to give predicted, optimized fault coverage for a board to be tested using JTAG/ boundary-scan. It also included a com- parative test feature to allow an actu- al coverage to be compared with the predicted state. This type of tool proved hugely successful, and allowed engineers to accurately quantify the effectiveness of boundary-scan, and advise when to augment test coverage with other methods. By 2001, the JTAG port was the


de facto standard mechanism for pro- gramming CPLDs and configuration PROMs. However, there was no for- mal standard for the data-formats used, or the instructions required to program parts. Later that year, a group of JTAG vendors and PLD sup- pliers was successful in gaining IEEE approval for the in-system con- figuration (ISC) standard, IEEE std. 1532. Unlike other popular program- ming formats, such as SVF, within this standard the data section was separate from the programming pro- tocol, which was now embedded with- in an extended syntax BSDL model. This allowed multiple devices in a scan chain, even from a mix of ven-


dors, to be programmed concurrently by merging their ISC files.


By the mid 2000s, the market expectation for


Some new high-speed memories are equipped to handle dot 6 test features.


ease of use in developing JTAG/boundary-scan testing saw a notable change. While the enthusias- tic early adopters of JTAG testing were accepting of systems that required some significant manual input and engineering ability, the later adopters of JTAG testing and programming demanded more automation and easier-to-use tools. ProVision soft- ware was one example of the second-generation of toolsets that relied less on user intervention and more on reusable models and maps to set up safe test conditions, and to cluster test opportunities. The program also offered a unified environment that supported boundary-scan structural testing, cluster testing, and the programming of CPLD, PROMs, NOR, and NAND flash. The modular approach of the system also meant that adding fur-


Continued on next page


Thermal systems for the electronic and photovoltaic industries


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