NEWS REVIEW Soitec launches 31.8% III-V solar module
SOITEC has announced its latest CPV module featuring a record power- generating effi ciency of 31.8 percent. The new module, which is already in industrial volume production, is claimed to deliver the highest effi ciency of any commercial product available for multi- megawatt installations.
Using an optimised anti-refl ective coating, Soitec’s CX-M500 module increases nominal peak power output over previous generations from 2,335 Wp to 2,450 Wp. The new module has been certifi ed according to the International Electrotechnical Commission’s (IEC) and Underwriters Laboratories’ (UL) standards (IEC 62108, IEC 62688, UL 62108 and UL SU 8703), confi rming that it meets product safety, performance and reliability requirements in both the US and European markets.
“With this new product, Soitec is continuing to raise the bar for solar- power effi ciency and, looking ahead, the potential for further improvement is signifi cant, “ says Gaetan Borgers, executive vice president of Soitec’s Solar Energy Division. “ Based on our current work in solar-cell development, we are well positioned to achieve even higher module effi ciencies in the near future. With our newest commercial modules and their higher effi ciencies, we are delivering on our cost-competitiveness roadmap. “
Soitec’s new module complies with the California Solar Initiative, so power- plant installations using it can qualify for performance-based incentives from the California Energy Commission (CEC). The module also bears the CE mark, indicating its compliance with the relevant European Union directives, regulations and standards.
Using Soitec’s III-V Concentrix technology, each Soitec CPV module comprises a Fresnel lens plate and a bottom plate on which high-performance solar cells are mounted. The Fresnel lenses focus sunlight concentrated by a factor of 500 on the solar cells beneath. The cells are precisely mounted on the bottom plate, enabling the focused sunbeam to align perfectly with the tiny solar cells. In constructing its modules, Soitec uses elements from the circuit board and dual pane window industries,
which are both cost effective and have been proven reliable over many years.
The modules are used in assembling Soitec CPV systems. Soitec’s tracker- based systems are designed to build high-capacity solar-power plants with low construction and maintenance costs. Soitec’s CPV systems can signifi cantly improve the Levelised Cost of Electricity (LCoE) for mid-sized to very large solar-power plants. With installations in 18 countries around the world, Soitec’s CPV technology has proven its
competitiveness to generate solar power, largely due to its higher production yields throughout the sunlight hours
CPV technology’s abilities to operate without cooling water, withstand hot ambient temperatures and have minimal environmental impact make it perfectly suited for use in environmentally sensitive desert areas. Soitec recently announced the signature of a performance-warranty insurance contract with Munich Re, which will ease fi nancing of solar projects using the company’s CPV modules.
New process could increase mobility beyond 10nm MOS devices
KULeuven, imec and AIST have developed a solid phase epitaxy process to integrate germanium tin (GeSn) metal-oxide semiconductor fi eld-effect transistor (MOSFET) devices on silicon.
For the fi rst time, operation of depletion- mode junctionless GeSn pMOSFET on silicon was demonstrated, which is a step toward achieving tensile strain in MOSFET devices, and increasing their mobility.
To improve performance in next- generation scaled complementary metal-oxide semiconductor (CMOS) devices, researchers are exploring the integration of novel materials with superior electron mobility. This includes GeSn, a promising semiconductor candidate as channel material, due to its superior physical properties.
GeSn enables increased switching speed of MOSFET devices and can be used in fast optical communication. While most prototype GeSn channel MOSFETs are fabricated on germanium substrates, silicon integration is preferred for CMOS compatibility.
However, epitaxial growth of GeSn on silicon substrates poses several challenges, including limited solubility of tin in germanium (0.5 percent), its compositional fl uctuations, tin segregation, and large lattice mismatch ( over 4 percent). Therefore, it is critical
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www.compoundsemiconductor.net October 2013
to suppress these effects to obtain high performance devices with GeSn layers.
Researchers from KULeuven, imec and AIST developed a solid phase epitaxy process, achieving ultrathin (greater than 10nm) single-crystalline GeSn layers on silicon substrates showing tensile strain, attractive for strain engineering of germanium channels.
TEM image of NiGeSn metal S/D MOSFET. TEM is observed along [11-2], the channel direction is [-110] and the surface orientation is (111)
This reduces the difference between the direct and indirect band transition, resulting in acquisition of a direct band gap group IV material. Lastly, due to its non-equilibrium deposition conditions, the new method enables the development of GeSn with high tin concentrations.
By decreasing the channel thickness with reactive ion etching (RIE) from ~30 to ~10nm, the researchers improved the on/off ratio by more than one order of magnitude.
Also, hole depletion in the ultrathin (~10nm) GeSn layers on silicon resulted in good transfer characteristics with an on/off ratio of 84. In the future, research will focus on optimizing the GeSn MOSFET on silicon devices to further increase the channel mobility.
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