industry VCSELs
thermal impedance cannot be made arbitrarily low to overcome the thermal limitation. Techniques that are well known for trimming thermal impedance, such as using binary material rather than ternary and quaternary alloys wherever possible, have already been incorporated in most 10 Gbit/s designs. Any further improvements in this area are limited, and may not be easy to implement.
Given that it is very difficult to push out the onset of thermal rollover, increases in bandwidth must come below the thermal limit. Such a design will be welcomed by many, because a faster device that consumes no more power than existing products will be highly valued in many applications. But how is it possible to make a VCSEL with a bandwidth that ramps up faster with bias current?
One approach is to reduce the optical mode volume, because this increases the photon density. An obvious way to realise this is to trim the aperture size, but this is not a great idea because smaller apertures increase current density and aggravate thermal bottleneck. Another option is to cut the cavity length, but there isn’t much headroom here, because the cavity in 10 Gbit/s designs is only one wavelength long. Further shortening is possible, but the gain is not sufficient in itself to spur VCSEL speeds to 25 Gbit/s.
New active regions Far greater gains are promised by selecting a better gain medium. Until now, active layers of commercial VCSELs have sandwiched GaAs quantum wells (QWs) with AlGaAs barriers. This design is easy to manufacture and has proven reliability, but to make the leap to 25 Gbit/s and beyond, the industry will have to abandon this traditional approach.
Our new design employs compressively strained QWs for higher differential gain, while maintaining an emission wavelength of 850 nm. Materials for both the QWs and the barriers have been carefully
chosen to produce an ideal level of strain, and the growth conditions optimized for performance and reliability. The number of quantum wells are chosen to maximise differential gain, and this judicious selection, plus the composition of the active region, promises to double differential gain.
When one roadblock to higher speeds is removed to any class of device, there is always the threat that another takes its place. With VCSELs, the danger is that parasitic elements become the new bandwidth bottleneck, but it is possible to prevent this from happening by minimizing pad capacitance (see Figure 2 for the VCSEL’s parasitic equivalent circuit). This has already been reduced to negligible levels in our 10 Gbit/s design and it has now become necessary to lower the oxide capacitance,
Our new design employs compressively strained QWs for higher differential gain while maintaining an emission wavelength of 850 nm. Materials for both the QWs and the barriers have been carefully chosen to produce an ideal level of strain, and the growth conditions optimized for performance and
reliability.The number of quantum wells are chosen to maximise differential gain, and this judicious selection, plus the composition of the active region, promises to double differential gain
October 2012
www.compoundsemiconductor.net 45
Fig.3.Reducing device parasitic elements,such as oxide capacitance, enables VCSELs to realise higher
modulation speeds
Page 1 |
Page 2 |
Page 3 |
Page 4 |
Page 5 |
Page 6 |
Page 7 |
Page 8 |
Page 9 |
Page 10 |
Page 11 |
Page 12 |
Page 13 |
Page 14 |
Page 15 |
Page 16 |
Page 17 |
Page 18 |
Page 19 |
Page 20 |
Page 21 |
Page 22 |
Page 23 |
Page 24 |
Page 25 |
Page 26 |
Page 27 |
Page 28 |
Page 29 |
Page 30 |
Page 31 |
Page 32 |
Page 33 |
Page 34 |
Page 35 |
Page 36 |
Page 37 |
Page 38 |
Page 39 |
Page 40 |
Page 41 |
Page 42 |
Page 43 |
Page 44 |
Page 45 |
Page 46 |
Page 47 |
Page 48 |
Page 49 |
Page 50 |
Page 51 |
Page 52 |
Page 53 |
Page 54 |
Page 55 |
Page 56 |
Page 57 |
Page 58 |
Page 59 |
Page 60 |
Page 61 |
Page 62 |
Page 63 |
Page 64 |
Page 65 |
Page 66 |
Page 67 |
Page 68 |
Page 69 |
Page 70 |
Page 71 |
Page 72 |
Page 73 |
Page 74 |
Page 75 |
Page 76 |
Page 77 |
Page 78 |
Page 79 |
Page 80 |
Page 81 |
Page 82 |
Page 83 |
Page 84 |
Page 85 |
Page 86 |
Page 87 |
Page 88 |
Page 89 |
Page 90 |
Page 91 |
Page 92 |
Page 93 |
Page 94 |
Page 95 |
Page 96 |
Page 97 |
Page 98 |
Page 99 |
Page 100 |
Page 101 |
Page 102 |
Page 103 |
Page 104 |
Page 105 |
Page 106 |
Page 107 |
Page 108 |
Page 109 |
Page 110 |
Page 111 |
Page 112 |
Page 113 |
Page 114 |
Page 115 |
Page 116 |
Page 117 |
Page 118 |
Page 119 |
Page 120 |
Page 121 |
Page 122 |
Page 123 |
Page 124 |
Page 125 |
Page 126 |
Page 127 |
Page 128 |
Page 129 |
Page 130 |
Page 131