technology  GaN HEMTs


The double heterostructure that we form consists of a 200 nm AlN nucleation layer; a buffer stack comprising 400 nm Al0.75 and 1800 nm Al0.25 and a 10 nm Al0.25


Ga0.25


Ga0.75 Ga0.75


Ga0.75 N, 400 nm Al0.50


GaN capping layer is deposited on top of the Al0.25


N4 pressure CVD (LPCVD) at 750 °C.


This structure yields reproducible, uniform two- dimensional electron gas (2DEG) characteristics across the wafer. According to measurements on Van-der-Pauw structures, the average 2DEG sheet resistance on 18 wafers with an identical epilayer stack is 360 Ω /, and the standard deviation is 5 percent (see Figure 1). Hall measurements reveal that the 2DEG carrier density is 8.9 x 1012 carrier mobility is 1950 cm2


cm-2 V-1 s-1 .


The AlGaN/GaN/AlGaN epilayer stacks that we deposit are about 3 µm thick, and they are formed on 1.15 mm-thick silicon substrates. These are thicker than standard substrates (which are 0.725 mm thick), because a greater rigidity is needed to obtain acceptable wafer bow and wafer brittleness. Processing at imec’s 200 mm CMOS silicon line demands a wafer bow of 50 µm or less.


Our epiwafers that are formed on 1.15 mm-thick silicon wafers are, in general, suitable for processing on production tools that have not been subjected to significant hardware or process modifications. Occasionally, however, we had to make adjustments to the tools, such as slowing down the robot speed of the wafer transport systems so that they can accommodate the larger inertia of thicker silicon substrates. We also avoided direct loading of the wafers on the electrostatic


Variations in wafer bow were tracked during device processing. Scrutinizing the data failed to uncover any significant addition to wafer bow during gate, ohmic, and aluminium interconnect processing. Adding thick copper interconnects introduces a tensile wafer bow, but this was limited to 40 µm or less. When modifications to the tools and bow monitoring were put in place, we experienced zero wafer loss during processing, according to standard fab operation procedures.


Preventing gallium contamination Processing wafers with compound semiconductor stacks on 200 mm silicon lines requires careful planning. Owners of these foundries may have concerns, such as the fear that gallium can contaminate the processing tools – it is a p-type dopant in silicon.


To determine whether there is genuine cause for concern, we adopted existing procedures for contamination control, while monitoring and controlling the spread of gallium from the GaN wafers to the tools. On most tools, gallium levels on the front and backside of silicon wafers are always below 1 x 1011


atoms/cm2 . One notable exception is


the tools that etch the GaN layers, which are used for processes such as the AlGaN barrier recess etch. In this case, gallium levels can exceed 10 x 1011


atoms/cm2 be held below 1 x 1011


. However, contamination can atoms/cm2


chlorine-based cleaning procedure at 200 °C that involves the formation of volatile GaCl3


.


Figure 1.imec’s engineers can produce structures with a reproducible,uniform AlGaN/GaN 2DEG sheet resistance.Data is for 18 epilayers grown on 200 mm silicon substrates


In the labs and fabs used to make GaN devices today, processing tends to involve lift-off metallization schemes for defining ohmic and gate contacts. These contacts are built from either the


October 2012 www.compoundsemiconductor.net 39 with an optimized and Ga0.50


N; a 150 nm GaN channel N barrier layer. A 2 nm-thick


N barrier to prevent it from cracking


during post-growth cool down. On that cap, we deposit a 120 nm Si3


passivation layer by low-


N


Figure 2.The threshold voltage of the MISHEMT is influenced by the barrier recess etch time.Enhancement mode devices are obtained for 60 s barrier recess.The inset figure shows the corresponding ID characteristics


-VGS


chuck of our implantation system – instead, we mounted them on carrier wafers to prevent them from breaking.


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