technology  GaN HEMTs


Figure 3.Cross-section scanning electron microscopy images of the power device.The top figure shows the source-gate-drain finger configuration, which has 8 µm-thick source and drain copper interconnect layer encapsulated by Si3


N4 .The bottom


picture details the source-gate area: The T-shaped metal gate electrode with the field plate,the gate dielectric,and the metallization stack in the ohmic source area


reduces local polarization charge. To recess the Al0.25


Ga0.75 N barrier, we used a BCl3


plasma at low bias


power. Etching for 0 s, 30 s, and 60 s led to barrier recess depths of approximately 0 nm, 5 nm and 0 nm respectively. A barrier recess etch time of 60 s produced positive threshold voltages of 1.0 V ± 0.2 V over the full 200 mm wafer (see Figure 2).


The gate leakage current of power devices can be suppressed by creating a MISHEMT structure in which a gate dielectric is inserted between the metal gate electrode and the AlGaN barrier to avoid the creation of a Schottky gate contact. However, we want to obtain devices with both a low gate leakage current and a high breakdown voltage, so the gate dielectric has to be carefully chosen.


pairing of nickel then gold or the combination of molybdenum then gold. In stark contrast, standard high-productivity CMOS fabs use gold-free metallization schemes, and dry etch patterning instead of lift-off.


It is a challenge to fabricate gold-free ohmic contacts with a contact resistance below 1.0 Ω mm. However, it is possible to get closer to this target with an AlGaN barrier recess in the ohmic areas, which is formed with a BCl3


/SF6


A fully processed 200 mm GaN-on silicon MISHEMT device wafer


plasma at low bias power. This yields a contact resistance of 1.25 ± 0.15 Ω mm when a 5 nm-thick AlGaN barrier remains. In comparison, contact resistances exceed 4 Ω mm when a barrier recess is not employed. Our gold-free Ohmic contact stack consists of 20 nm of titanium, followed by 100 nm of aluminium, another 20 nm of titanium and 60 nm of TiN. This is alloyed at 550 °C for 90 s in a nitrogen gas atmosphere.


Further reading


K. Cheng et al., Appl. Phys. Express 5 011002 (2012) M. Van Hove et al. IEEE Electron Device Lett. 33 667 (2012) B. De Jaeger et al. Proceedings of 24th International Symposium on Power Semiconductor Devices and ICs, Bruges, Belgium, 3-7 June 2012, p. 49.


Device demonstrations To showcase the feasibility of processing AlGaN/GaN HEMTs on 200 mm GaN-on-silicon wafers, we have fabricated fully functional power devices with a 60 mm total gate width.


There are a wide variety of device architectures available to us, which could realise either depletion- mode (d-mode) or enhancement-mode (e-mode) power devices. We decided to focus on the latter class of device because this is a promising candidate for making reliable, high-performance, high-breakdown GaN power devices with normally off characteristics. Specifically, we fabricated an e-mode AlGaN/GaN metal-insulator-semiconductor HEMT (MISHEMT) with barrier recess and gate dielectric.


E-mode operation results from sufficiently recessing the AlGaN barrier in the gate areas, a step that


40 www.compoundsemiconductor.net October 2012


Power devices that we have produced as described above have a total gate width of 60 mm and consist of 60 gate fingers of 1 mm each. Gate length is 1.5 µm, gate-source distance is 0.75 µm and gate- drain distance is 10 µm. By extending the gate metallization by 1 µm to the drain side, we formed a gate-connected field plate. The devices delivered a maximum output current of 6 A at VGS VDS


= 8 V and


= 10 V. These results demonstrate the feasibility of AlGaN/GaN HEMT processing on 200 mm silicon substrates.


Our next step is to improve the characteristics of these transistors. At present, their performance lags that of our HEMTs made on 150 mm silicon wafers, which have a maximum output current of 8 A, a breakdown voltage of 750 V, a specific on- resistance of 2.9 mΩ cm2 leakage at 600 V of 7 µA.


and an off-state drain


There are no obvious barriers to replicating these results on 200 mm silicon wafers, and when we do that it will strengthen our claim that GaN-on-silicon wafers can combine affordability with a great set of characteristics. Silicon may be in the ascendancy in the market today, but it is going to face an ever increasing threat to its supremacy place from GaN-on-silicon power electronics.


© 2012 Angel Business Communications. Permission required.


Starting with a single layer of 15 nm atomic layer deposition (ALD) Al2


O3 N4 and 10 nm ALD Al2 O3 , we measured breakdown


values below the 600 V target. But with a bilayer of 5 nm 650 °C LPCVD Si3


, we


measured breakdown values above 600 V, close to the buffer breakdown values. This improved breakdown is most probably related to the higher- quality of the semiconductor/dielectric interface obtained with the Si3


N4 /Al2 O3


bilayer (see Figure 3).


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