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March, 2020

Scanning Acoustic Microscopy Analyzes 3D Packages in the Z-Dimension

By Jeff Elliott T

he concept behind advanced 3D packaging is to stack multiple die or wafers in a vertical direc-

tion — or z-dimension — to achieve better performance with lower power requirements, smaller size and lower cost.

However, as 3D packages be -

come increasingly complex, so do the challenges of identifying defects in multiple layers of stacked die, silicon interposers and interconnections, such as through-silicon vias (TSVs) and fine-pitch micro-bumps. With less accessibility to inter-

nal components and a need to scan multiple, stacked layers, the focus is now shifting to methods of nonde- structive testing both in manufactur- ing and for failure analysis.

3D Advanced Packaging In general, the term 3D packag-

ing applies to products manufactured by stacking silicon wafers or die and interconnecting them vertically. This covers many integration schemes, including 3D wafer-level packaging, system in package (SiP), package on package (PoP), 2.5D and 3D, stacked ICs, and other forms of heteroge- neous integration. To achieve vertical stacking,

early 3D packages relied on intercon- nects such as wirebonding and flip chips. Today, communication be - tween chips often involves a silicon or organic interposer or bridge, with TSVs. The interposer acts as the bridge between the chips and the board, while increasing the I/Os and bandwidth. Now, the concept of chiplets is

gaining momentum for advanced packaging. In this approach, modu- lar chips — or chiplets — from third- party vendors are used to build a package or system by stacking the components vertically. By selecting the optimum CPU,

IO, FPGA, RF or GPU, for example, the chiplets could be mixed and matched using a die-to-die intercon- nect scheme involving a silicon inter- poser, a silicon bridge or high-densi-

ty fan-out. This approach has been em -

braced by Intel, which recently announced its new Foveros 3D pack- aging technology that allows com- plex, heterogenous logic chips to be stacked directly on top of each other.

ecosystem of discrete modular, reusable IP blocks, which can be assembled into a system using exist- ing and emerging integration tech- nologies,” writes Andreas Olofsson in program information posted on the DARPA website.

poor interconnection can render the entire 3D package nonfunctional. This is driving the requirement for 100 percent inspection during manu- facturing, ideally with nondestruc- tive testing methods.

Nondestructive Testing of 3D Packages

The challenge today is to per-

form 100 percent inspection with rel- atively high throughput to identify and remove 3D packages or compo- nents that do not meet quality requirements. Among the available nonde-

structive methods, scanning acoustic microscopy (SAM) is the most widely used techniques for testing and fail- ure analysis involving stacked die or wafers.

SAM utilizes ultrasound waves

PVA TePla offers a range of scanning acoustic microscopy tools. Intel uses an active interposer

instead of a typical passive silicon interposer. As an alternative, Intel is also offering its silicon bridge tech- nology called embedded multi-die interconnect bridge (EMIB). The Defense Advanced Research

Projects Agency (DARPA), an agency of the U.S. Department of Defense, already plans to develop a large cata- log of third-party chiplets for commer- cial, military and aerospace applica- tions.

The goal of DARPA’s CHIPS

program (Common Heterogeneous Integration and Intellectual Property Reuse Strategies) is to increase over- all system flexibility and reduce design time by as much as 70 per- cent.

“The vision of CHIPS is an

to nondestructively examine internal structures, interfaces and surfaces of opaque substrates. The resulting acoustic signatures can be construct- ed into 3D images. These images are analyzed to detect and characterize flaws, such as cracks, delamination, inclusions, and voids in bonding interfaces, as well as to evaluate sol- dering and other interface connec- tions.

Still, there are challenges to

making the chiplet concept work, including how to verify and test the individual chiplets from a variety of third-party vendors. Integrating multiple chiplets into stacked, 3D packages also requires high-density interconnections, all of which are potential sources of failure. In comparison to other 3D pack-

age types, for example, stacked die with TSVs require much smaller, finer pitch solder bumps that create additional challenges in defect detec- tion. Any defective chiplets in the package will result in a nonfunction- al package, even if all other modules are functional. Given the combined value of the chiplets, interposer and other compo- nents, a single defective chiplet or

The unique characteristic of

acoustic microscopy is its ability to image the interaction of acoustic waves with the elastic properties of a specimen. In this way, the micro- scope is used to image the interior of an opaque material. SAM works by directing focused

sound from a transducer at a small point on a target object. The sound, hitting a defect, inhomogeneity, or a boundary inside material, is partly scattered and will be detected. The transducer transforms the reflected sound pulses into electromagnetic pulses which are displayed as pixels with defined gray values, creating an image.

To produce an image, samples

are scanned point by point and line by line. Scanning modes range from

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