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Chip carrier packaging grows thanks to QFN

ADVANCED PACKAGING of semiconductor chips has emerged as a key enabler in many of today’s electronic system products. Put another way, package selection is increasingly important to the success of the end product.

While much attention with regard to IC packaging is on 3D stacking and integration technologies, there is another area of packaging that has quietly been flourishing during the past decade and a half.

Introduced in 1998, the quad flat no-lead (QFN) package design (including the related dual-sided DFN) has enjoyed phenomenal growth from the very beginning. With its low cost, small size, and excellent thermal and electrical performance characteristics, the QFN quickly became the mainstream package of choice for many low-to-medium I/O count ICs.

In the past decade, new dual-row and even triple-row technologies have enabled QFNs to support many more I/ Os and, thus, enter a wider range of IC product segments. Today, the QFN is one of the most widely used IC package types.

IC Insights forecasts that the continuous high growth in demand for QFN-type packages will help push the flatpack/chip carrier (FP/CC) category of packages past the “old” small outline (SO) group of packages for the first time ever in 2013, as shown in the figure below.

The QFN is a type of chip carrier. The SO packages emerged in the early 1980s and then grew to become the industry’s most widely used package type by 1995. The FP/CC packages emerged around the same time and they offered higher I/O capabilities than the SO packages because they had leads on all four sides.

The QFN package category in the JEDEC standards includes a variety of manufacturer-specific designs such as the MicroLeadFrame (MLF) package from Amkor, Fujitsu’s Bumped Chip Carrier (BCC) and small outline no-lead (SON)

packages, Carsem’s Micro Leadframe Package (MLP), and ASE’s microchip carrier (MCC).

There are similar JEDEC standards for DFN packages that have external bond pads or “lands” on two sides instead of four like the QFN. Besides being categorised in the FP/CC group of packages, QFNs and DFNs are also considered part of a larger group of packages called leadframe CSPs, or chip-scale packages.

QFN and DFN packages are inexpensive to manufacture. They typically don’t have solder balls, are targeted at low-I/O applications (typically less than 85), and make use of pre-plated leadframes. Either wirebonds or flip-chip bumps are used to attach the IC to the leadframe.

Versions like the MLF and BCC have an exposed die-attach paddle on the bottom of the package, which serves as an excellent thermal path away from the chip as well as a good ground-plane if the pad is grounded on the circuit board.

That, in conjunction with the high electrical performance offered by short I/O connections, has made these leadframe CSPs attractive for use in packaging RF circuits for cellphones and other wireless and portable product applications.

Many companies have migrated from SO-type packages to QFNs and DFNs and their popularity continues to spread as new advancements make QFNs/DFNs capable of handling a greater amount of circuitry and functionality.

10 Issue IV 2013 TSMC &

Imagination to drive GPUs

IMAGINATION TECHNOLOGIES is working with TSMC to drive next- generation performance to new levels on Imagination’s PowerVR GPUs.

Initial efforts have already achieved 25 percent overall performance improvements for the PowerVR Series6 GPU core, with key blocks demonstrating as much as 30 percent improvement compared to existing design flows.

Imagination R&D teams working with TSMC are developing IP libraries and fully characterised reference system designs for Imagination’s IP cores on TSMC’s advanced processes including 28HPM and 16nm FinFET technologies. This collaboration will enable mutual customers to achieve significant performance gains for next- generation applications.

Imagination is tapping out an optimised next-generation multi- core, multi-cluster PowerVR Series6 GPU design to characterise these performance improvements and plans to demonstrate a test chip later this year.

The resulting reference flow and optimised libraries will enable SoC designers to significantly accelerate time-to-market and increase performance for similar implementations of PowerVR Series6 GPUs.

Tony King-Smith, Imagination EVP marketing says, “The growing reliance on graphics processors to power the best user experiences means the GPU has become the new silicon process driver for the coming decade. It occupies as much as 50 percent or more of leading edge SoCs, and demands the highest performance memory bandwidth while always delivering high performance at low power. These characteristics are critical to defining the key device parameters of future generation processes.

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