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Samsung mass producing 20nm-class DDR4 memory chips

SAMSUNG ELECTRONICS is mass producing, what it claims, is the most advanced DDR4 memory chips, for enterprise servers in next-generation data centres. With the introduction of these high-density DDR4 modules, Samsung can better support the need for advanced DDR4 in rapidly expanding, large-scale data centres and other enterprise server applications.

Early market availability of the 4-gigabit (Gb) DDR4 devices, which use 20 nanometre (nm)-class process technology, will facilitate demand for 16-gigabyte (GB) and 32GB memory modules. This compares to conventional DRAM of which 8GB modules using a 30nm-class process technology are still commonplace.

“The adoption of ultra-high-speed DDR4 in next-generation server systems this year will initiate a push toward advanced premium memory across the enterprise,” says Young-Hyun Jun, executive vice

president, memory sales & marketing, Samsung Electronics. “After providing cutting-edge performance with our timely supply of 16GB DDR3 earlier this year, we are continuing to extend the premium server market in 2013 and will now focus on higher density and added performance with 32GB DDR4, and contribute to even greater growth of the green IT market in 2014,” he adds.

In next-generation enterprise servers, the use of higher speed DRAM raises system level performance and lowers overall power consumption significantly.

By adopting DDR4 memory technology early, OEMs can minimise operational costs and maximise performance to provide more favourable returns on investments. Production of Samsung’s 20nm-class 4Gb DDR4 follows the introduction of 50nm-class 2Gb DDR3 in 2008, culminating in a fully fledged transition to DDR4 for large-scale data centres and other enterprise applications in just five years.

Samsung says the 4Gb-based DDR4 has the fastest DRAM data transmission rate of 2,667 megabits per second - a 1.25- fold increase over 20nm-class DDR3, while lowering power consumption by more than 30 percent. Based on Samsung’s 20nm-class DRAM compact 4Gb DRAM chip, the company has now developed a new series of products tailored to applications from servers to mobile devices. This will provide global customers with the widest range of highly advanced low-power, high-performance green memory solutions.

Process to improve 3D-IC / TSV packaging reliability

revealed to industry EV Group (EVG)has developed a new polymer via-filling process for 3D-IC/ through-silicon-via (TSV) semiconductor packaging applications.

Available on the EVG100 series of resist processing systems, the new NanoFill process provides void-free via filling of very deep trenches and high-aspect ratio structures, and is suitable for all common polymeric dielectrics-offering a highly flexible, low-cost and production- ready via-fill platform for interposer development for 3D-integrated image sensors and other device types.

TSV interconnects are critical to the development of 3D-ICs since they enable through-chip communication between the vertically stacked device layers. Currently, most TSVs employ a solid copper via structure.

However, the mismatch in coefficient thermal expansion (CTE) between the copper via and the surrounding silicon

can create a high amount of stress on the via structure, which results in long-term reliability issues.Replacing copper as the conducting material is not practical due to the general ease of use of the process. Also, the tooling infrastructure for copper is already well established.

However, replacing the solid copper via with a partial copper-plated via that is filled with a polymeric dielectric has been demonstrated to reduce CTE mismatch and stress, thus minimising reliability issues.

EVG’s proprietary process and system enable simultaneous void-free via filling and dielectric redistribution layer (RDL) formation utilising a field-proven process technology that is compatible with all standard polymeric materials.

“3D packaging represents a fundamental change in the semiconductor industry that paves the way for continued advances in device performance and

cost reduction through ‘More than Moore’ approaches,” states Markus Wimplinger, corporate technology development and IP director at EV Group.

“EV Group has made significant investments in our portfolio of wafer-level manufacturing solutions to add new products and capabilities, such as our NanoFill solution, to help our customers accelerate the commercialization of 3D-integrated devices.”

Issue IV 2013 11

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