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MATERIAL ADVANCEMENTS


Additionally, a compatible SnAg counterpart to the Cu pillar chemistry has been developed, resulting in a formulation that demonstrates high speed plating (>3µm/min); highly uniform SnAg deposits; (WID <±5% for challenging fine-pitch die designs); macro and micro void-free performance (X-ray); smoother surface morphology (as-plated and post-reflow) and a smoother, void-free interface with Cu pillar compared with its predecessors. Overall, this material exhibits the widest process window with the most robust process flexibility and a competitive COO.


Temporary bond/debond


In 3D IC development, the temporary bond and debond step has provided ongoing obstacles and continues to be considered a roadblock to commercialization. Materials must meet temperature stability and chemical resistance requirements due to the various process steps that a bonded wafer pair undergoes -- from the time of application to the process wafer, through the backside thinning and processing, debonding and cleaning.


The adhesive used to create a temporary bond should have certain attributes to be considered practical. For example, the adhesive has to survive several processes that will inflict environmental extremes. The bond has to be strong enough to support the wafer through the thinning process, but easily debonded when needed without damage to the wafer or the electronic devices. The debonding must be gentle since the wafer is so fragile and any remaining residue needs to be easily removed.2


While many materials on the market have achieved many of these attributes, the gating technical issue has been with the debonding step. One solution that has recently been developed is based on a well-established permanent bonding adhesive. This benzocyclobutene (BCB) material offers inherently attractive material properties such as high thermal stability (withstanding temperatures up to 300°C), high chemical resistance and low temperature curing. It has been successfully modified to make it easily releasable from various surfaces, allowing it to be used effectively as a temporary bonding adhesive.


Clean debonding is critical, and this one requires no additional process steps for removal from the active die surface, such as laser/UV ashing or solvent soaks. Rather, an adhesion promoter is spin-coated onto the carrier wafer so that when it is debonded


using mechanical lift-off at room temperature, the adhesive goes with the carrier and leaves the device wafer free of adhesive material (Figure 2). In the event of bumped wafers, a solvent rinse may be required to remove any minor residue.


Another advantage of the modified BCB material is that while it withstands high temperatures (>300oC/1 hr), it bonds at low temperatures, which eliminates bonder/heater time and increases wafer throughput. Final cure is then performed in a batch oven process outside the bonder with no alignment shift, for increased throughput and reduced COO.


Pre applied underfill


Underfilling 3D IC stacks is critical to help control TSV-induced stress and also to help control warpage of these ultra-thin stacks caused by CTE mismatch between the device and its substrate. In fact, thermal modeling and simulation studies show that underfill, substrate and mold compound thermal strains play important roles in the warpage evolution.3


After backside processing, thin devices must be assembled into stacked-die structures. Current underfill technologies required for assembly have issues with voiding and have been known to result in filler entrapment during bonding. Additionally, there have been issues with bleed and creep of underfill around the die, particularly with today’s finer pitch geometries.


Alternatively, pre-applied underfills allow for simultaneous electrical and adhesive die bonding. One such material has performed well when applied as a wafer-level underfill for bonding Cu pillars with 25µm diameter and 50µm pitch on thinned die.


When applying via vacuum lamination to 300mm wafers, the result is good uniformity and thickness. It also addresses the fine pitches required for stacking logic SoCs with TSVs; an application where capillary underfills fall short. Test vehicles have demonstrated 100 % electrical joining after thermocompression bonding (Figure 3).


Figure 2: Even dense, C4-bumped wafers debond cleanly: SnAg solder bumps after debonding (left), BCB-based temporary bonding adhesive film after debonding (right, below)


32 www.siliconsemiconductor.net Issue IV 2013


Low stress high performance dielectrics As previously mentioned, increased stress and wafer bow is also an issue due to the thinner substrates required for vertical integration in TSV and 3D packages. In addition to underfill materials and molding compounds, cured dielectric materials also contribute to the condition. Recent developments extending the thermal, electrical and chemical stability of BCB-based materials have resulted in a lower residual stress prototype of a photodielectric that is currently used in high- volume manufacturing


Figure 3: 100 % electrical joining of 1600 solder joints per daisy chain


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