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THE EXPLODING MOBILE MARKET is driving feature requirements for next-generation semiconductor devices to increasingly smaller geometries. As a result, there is increased risk of wafer stress due to more delicate features, thinner wafers to handle, and in the case of 3D IC technologies, higher density through silicon vias (TSVs) and the need to accommodate microbump structures. Equipment and processes can only go so far with existing material sets initially developed for the last generation of packages before they hit process limitations. The task has fallen largely on the shoulders of material science to tackle these limitations with novel and innovative chemistries.

Fortunately, as the entire semiconductor packaging ecosystem has entered a new age of cooperation and transparency, collaboration with R&D centers and partnerships with equipment suppliers have resulted in significant developments across the spectrum of advanced packaging materials to meet these new challenges. This article will present a number of recent technology breakthroughs including compatibility of metallurgies for tin silver (SnAg) capped copper (Cu) pillars; advancements in temporary bond/debond adhesives that allow for clean debond from active device wafers at room temperature; pre-applied underfill for die stacking that addresses the fine pitches required for stacking logic system- on-chips (SoCs) with TSVs; and low stress, high performance dielectrics that address increased stress and wafer bow resulting from thinner substrates. These material advancements began with either new material formulations or proven materials that have been optimized to address the emerging requirements of next-generation devices.

SnAg-capped cu pillars With mobile device manufacturers clamoring for higher density, fine-pitch ICs, a trend to replace conventional flip chip solder bumps with Cu pillar bumps capped with SnAg solder has emerged. This is because SnAg capped Cu pillars enable the higher density interconnects and lower profiles needed for emerging 2.5D interposer and 3D packaging applications. Devices that have made the transition to SnAg capped Cu pillars include high-end graphics processors, FPGAs, power amplifiers, MEMS and HB-LEDs.

In particular, silicon interposers and fine-pitch Cu pillar micro- bumps represent the two technologies that have come to define a 2.5D packaging approach. Cu pillars provide the short, low inductance, efficient interconnections between ICs in vertical stacks as well as between an IC and the silicon interposer. Capping Cu pillars with SnAg allows for improved reflow with the silicon interposer, achieving <40µm pitches. Together, micro-bumps and silicon interposers provide a high-speed and high-bandwidth communication highway for side-by-side die (and stack) placement.1

When selecting materials that will result in high-yield, reliable electroplated Cu pillar and Cu µpillar capped structures, it

Table 1: Comparison data between a commercially available product and a new Cu Pillar formulation

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Figure 1: Left, Cu µpillar with SnAg cap as plated. Right, Cu µpillar with SnAg cap post reflow

is important to consider the interface between metal layers, particularly as Cu pillar cap diameters shrink to µpillar dimensions (<30µm diameter). Additionally, interfacial properties and intermetallic compounds (IMCs) must be understood and controlled. The plating chemistry has significant influence on the compatibility of each layer, as well as control of IMC-growth, micro-void formation and overall stack reliability.

In designing chemistries, the compatibility of the Cu and solder materials is of critical importance. This compatibility is evidenced by such characteristics as a smooth, continuous IMC layer formed after reflow of Cu pillar and Cu µpillar with SnAg solder caps (Figure 1). The dominant IMC formed is Cu6


between the Cu and SnAg interface after reflow. IMCs make up a significant fraction of the SnAg cap for Cu µpillar bump. Additionally, no interfacial voiding should be observed after reflow.

Further, industry needs for higher throughput, smaller, finer pitch features and low cost of ownership (COO), in addition to requirements for flatter pillars with smooth surface and good uniformity, is driving further development work on next- generation Cu pillar and SnAg chemistries.

The most recently developed formulations have satisfied all key design criteria including highly uniform Cu pillars (within die (WID) < 5%); a flat pillar profile (total indicated runout (TIR) < 5%); smooth surface morphology; and compatibility with SnAg capping (Table 1).

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