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February, 2018
Design-for-Testability Verified with Hardware Emulation Continued frompage 60
First, it decreased the duration
of the test cycle. Second, it eased the complexity of test/probe set up, by shrinking the number of I/O signals that must be driven/examined under tester control. Further, BIST made it possible to test circuits at speed (at GHz),
area and more verification cycles (as pseudorandom), but saves the cost of generating and storing test vectors. Also, BIST often takes less time as it can be run at full clock rate.
DFT Verification Scan and BIST are usually
incorporated in the design after it has been verified to be functionally cor-
creates the necessary testing infra- structure for reading test vectors from the STIL file, applying them to the synthesized DUT, and for com- paring the outputs. The compiler also re-compiles and synthesizes the user netlist into a structural description compatible with emulation. The DFT app enables execution
of complete pattern sets for DFT veri- fication in a reasonable time to short- en the pattern development cycle. Scalable hardware and a compiler enables test pattern validation for large gate-level designs with scan and other test structures embedded into
the design. The DFT app is interoper- able with other tools, by supporting standard STIL format files. An emulation session provides
enough verification power to pull the DFT schedule within the time the project management has scheduled. This powerful tool can accelerate time-to-market, increase the yield and ultimately raise profits. Contact: Mentor, A Siemens
Business, 8005 SW Boeckman Road, Wilsonville, OR 97070 % 503-685-7000 E-mail:
tessent@mentor.com Web:
www.mentor.com r
During runtime, the Veloce Emulator fetches test vectors from
the STIL file, applies them to the DUT and compares the output at emulation speed.
leading to more thorough examina- tions.
The basic approach was to com-
press “good” test responses into a “signature” and implement pseudo- random (or pseudo-exhaustive) pat- tern generators (PRG) onto the chip. BIST is indeed the integration of pat- tern generation and response evalua- tion on the chip. In the most popular BIST
methodology, scan cells are modified to generate pseudorandom test vec- tors at the input to a logic block, and then to collect a signature at the out- put, using a linear feedback shift reg- ister (LFSR). Examples of BIST in - clude LFSR and MISR (multiple-sig- nature input register) used to gener- ate the signature of the tested circuit. BIST consumes more silicon
rect. Unfortunately, the insertion of the on-chip test infrastructure, such as scan chain, BIST structure and compression/decompression logic, may interfere with its functional cor- rectness. It is essential to perform a gate-level verification of the design, after the DFT implant. Right off the bat, HDL simula-
tion cannot do the job. Given the level of design complexity, gate-level simu- lation would require many months — or years — for complete verification. This task is a perfect match for a hardware emulation platform.
Emulation with a DFT App Mentor Graphics offers a DFT
“app” for hardware emulation that includes everything necessary to achieve this objective. Its compiler
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SH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 21 22 23 24 25 26 27 28 29 30 16 17 31 32 33 34 35 36 37 38 39 40 41 42 43 44 M A T C H D A T A 1-6-18 10:57 AM
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SH 31 32 33 34 35 36 37 38 39 40 41 42 43 44 21 22 23 24 25 26 27 28 29 30 5 6 7 8 9 10 11 12 13 14 15 16 2 3
Designing the Future’s Inspection Machines
Continued from page 58
SMT Assembly. For SMT assembly, the company pro- vides solutions to meet nearly any need in the industry. Built on the experience of the com- pany in the front-end and back-end semiconductor mar- kets, MVP can now provide the same techniques, resolu- tions, and 3D tools to SMT manufacturers. The company faces new
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N E T L I S T
L-SH L-1 L-2
-L-3 L-4 L-6 L-7 L-8 L-9
L-10 L-11 L-12 L-13
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R-SH L-17 R-2
+R-3
L-5 R-5 R-6 R-7 R-8 R-9
R-10 R-11 R-12 R-13
N O T E S
Z-AXIS CONTROLLER CABLE Connector Type: High-density Dsub, 44 pins. Connector must have machined pins and metal shell. Use AMP part 778224-6.
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