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February, 2018
Design-for-Testability Verified with Hardware Emulation
By Dr. Lauro Rizzatti, Verification Consultant
a good device, you shoot yourself in the foot, since you lower the yield of your manufacturing facility and take a hit to profits. But, if you pass a failing device, the undetected manufacturing flaw will eventually be found in the field at a cost several times higher than on the manufacturing floor, impacting profits and, worse, your reputation with customers. This is still true today, and in fact, it has just
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gotten worse. Recent statistics reveal that the cost of testing a batch of chips after manufacturing, in order to determine which parts are free of defects (as opposed to free from design bugs), adds up to 40 percent of the cost of building the chip. These considerations drove the industry to
devise methods to build testability into the chip at the design stage, aimed at lowering the testing costs. Called design-for-testability (DFT), it is pos- sible to ensure the detection of all faults in a cir- cuit, reduce the cost and time associated with test development and to reduce the execution time of testing fabricated chips. Broadly speaking, over time, the industry
developed two forms of DFT: ad hoc and struc- tured. Ad hoc DFT consists of a set of rules to pro- mote “good” design practices to ease and accelerate the testing process. Examples include making all flip-flops initializable by providing set and reset signals, avoiding asynchronous logic feedbacks that can result in oscillation, eschewing gates with a large fan-in, since they make the inputs difficult to observe and outputs difficult to control. Or, pro- vide test control for difficult-to-control signals. For example, signals produced by a long
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With a DFT app, user inputs are fed into the hardware emulation’s compiler. The emula- tor then creates a representation of the DUT.
Structured DFT: Scan and BIST Structured DFT involves adding extra logic
for test according to some procedure. The most commonly-used structured methods are scan and built-in-self-test (BIST). Scan was first mentioned by Williams and Angell in 1973. Sequential cir- cuits — as opposed to combinatorial designs — are difficult to test. The main idea behind scan was to make the internal memory elements part of a shifter register chain to provide controllability and observability through serial shifts. With scan chain, the problem of testing any
circuit is reduced to testing the combinational logic between registers. The basics are to convert each flip-flop to a scan register. The only cost is one extra
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n the production/testing floor, is it better to pass a failing device or to reject a good one? Obviously both are bad choices. If you reject
counter require many clock cycles to control, which increases the length of the test sequence. Generally speaking, ad hoc DFT does not add logic, meaning it does not consume silicon in the design.
multiplexer. In normal mode, flip-flops behave as usual. In scan mode, they behave like a shift regis- ter. The contents of flops can be scanned out and new values scanned in. More to the point, the method allowed the development of automatic test pattern generators (ATPGs), and alleviated the time-consuming and tedious task of creating test vectors. As circuit complexity increased over time,
VLSI designs in the 1990s and in the new millen- nium of SoC chips, tester costs surged dramatical- ly as did the cost of test program development. An extremely high and ever-increasing logic-to-pin ratio on the chip makes it harder to accurately con- trol and observe the inner workings of the device — essential for testing. Consider these difficulties:
l l l l l
SoC devices are increasingly denser and faster with each drop in process technology node.
Test pattern generation and application are becoming extremely long.
It is increasingly difficult and expensive to perform at-speed testing (at GHz).
Prohibitive amounts of test data must be stored in the ATE.
Unfamiliarity with gate-level structures of the DUT, since logic is now automatically synthesized from hardware description languages (HDLs), thus compounding the problem of testability insertion.
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Dramatic lack of skilled test engineers. To cope with this unstoppable trend, the
industry responded by integrating some tester capabilities onto the chip, hence the name BIST. BIST reduced the complexity, decreasing the cost and reliance upon external (pattern-programmed) test equipment in two ways.
Continued on page 62
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