RESEARCH HIGHLIGHTS
Nanowire electronics Seamless memory
Vertical silicon nanowires prove to be an excellent platform for nonvolatile memory devices without the need for doped junctions
As electronic devices become smaller and more sophisticated, the search for compact nonvolatile memory becomes increasingly important. However, conventional silicon technologies, such as complementary metal-oxide-semiconductor (CMOS) and floating gate flash memory, are fast reaching their scaling limit. Further miniaturization could seriously affect their performance and stability. Navab Singh and co-workers at the A*STAR Institute of
Microelectronics and the Nanyang Technical University of Singapore have now created a highly scalable method for storing data using vertical nanowires1
. Their device contains none of the
‘junctions’ commonly used in conventional silicon technologies and has a much smaller footprint. In a CMOS device, a junction is the boundary of a p-type and
an n-type semiconductor created by adding functional impuri- ties selectively into the semiconductor crystal. In the new device, Singh and co-workers created an ‘electrical’ junction by carefully selecting the gate material based on their work function and eliminating the need for any doped junction inside the silicon nanowires. The charges are stored in a nitride thin film sand- wiched between the surrounding gate and the wire, separated by thin oxide layers on both sides. “The nanowires are uniformly doped without junctions and
conduction through them is controlled by a gate surrounding their central portion,” explains Singh. “The gate material is selected such that when there is zero potential applied on the gate, the wire is fully depleted of carriers and the current cannot flow, creating an OFF state.” The amount of charge tunneled into the nitride from the
nanowire also influences the current through the wire. The dif- ferent current values, namely ‘high’ or ‘low’, caused by different numbers of charges trapped and their position in the nitride, signify different data bits. “Our devices, being vertical, enjoy multi-bit data storage per
cell because charges trapped at different locations in the nitride do not interfere with each other, meaning they can remain far apart even with aggressive scaling of the footprint,” says Singh. “Such interference has been one of the key challenges in scaling
A*STAR RESEARCH OCTOBER 2011– MARCH 2012 77
the flash memory. Furthermore, we can put multiple cells on a single wire like a multi-storey building, allowing even more bits being stored per nanowire.” The devices are sensitive to variations, so the researchers had
to run the process under tight controls. In particular, the vertical nanowires must be uniform in shape due to differences between the top and bottom storage bits if tapered. Despite these challenges, Singh believes the junction-
less system may hold the key to future memory storage for data centers, computers and mobile devices. What’s more, by removing the doped junctions, devices could be much simpler and cheaper to make.
1. Sun, Y. et al. Junctionless vertical-Si-nanowire-channel-based SONOS memory with 2-bit storage per cell. IEEE Electron Device Letters 32, 725–727 (2011).
■
©
iStockphoto.com/RuslanDashinsky
Page 1 |
Page 2 |
Page 3 |
Page 4 |
Page 5 |
Page 6 |
Page 7 |
Page 8 |
Page 9 |
Page 10 |
Page 11 |
Page 12 |
Page 13 |
Page 14 |
Page 15 |
Page 16 |
Page 17 |
Page 18 |
Page 19 |
Page 20 |
Page 21 |
Page 22 |
Page 23 |
Page 24 |
Page 25 |
Page 26 |
Page 27 |
Page 28 |
Page 29 |
Page 30 |
Page 31 |
Page 32 |
Page 33 |
Page 34 |
Page 35 |
Page 36 |
Page 37 |
Page 38 |
Page 39 |
Page 40 |
Page 41 |
Page 42 |
Page 43 |
Page 44 |
Page 45 |
Page 46 |
Page 47 |
Page 48 |
Page 49 |
Page 50 |
Page 51 |
Page 52 |
Page 53 |
Page 54 |
Page 55 |
Page 56 |
Page 57 |
Page 58 |
Page 59 |
Page 60 |
Page 61 |
Page 62 |
Page 63 |
Page 64 |
Page 65 |
Page 66 |
Page 67 |
Page 68 |
Page 69 |
Page 70 |
Page 71 |
Page 72 |
Page 73 |
Page 74 |
Page 75 |
Page 76 |
Page 77 |
Page 78 |
Page 79 |
Page 80 |
Page 81 |
Page 82 |
Page 83 |
Page 84 |
Page 85 |
Page 86 |
Page 87 |
Page 88 |
Page 89 |
Page 90 |
Page 91 |
Page 92 |
Page 93 |
Page 94 |
Page 95 |
Page 96