RESEARCH REVIEW Dislocation-free GaAs on silicon
offers a route for scaling CMOS Etching silicon to create a trench with silicon {111} planes enables the growth of dislocation-free GaAs
MAINTAINING THE MARCH of Moore’s Law throughout this decade and beyond will require a switch from silicon channels to those sporting higher mobilities. Making this modification will allow devices to maintain their speed while working at a lower operating voltage, and will ultimately enable a scaling of power consumption per transistor.
III-Vs are very promising candidates for realising higher electron mobilities, but forming them on silicon substrates – the only platform suitable for microprocessor manufacturing – is very tricky, due to lattice mismatches and differences in polarity between the two types of material. However, success is possible, according engineers from imec. This team has developed a reproducible process for forming dislocation-free, 40 nm- wide GaAs trenches with good uniformity across 300 mm silicon substrates.
According to corresponding author Weiming Guo from imec, although the academic literature contains reports of III-V material with small dimensions integrated on silicon, it is rare to find a description of a procedure suitable for industrial mass production. “Our work reveals an interesting way towards this goal.”
Using GaAs, rather than InP, as a foundation for transistors may raise a few eyebrows, as the standard structure for a III-V FET is an InGaAs channel on an InP buffer. However, it is challenging to grow InP and related materials when dimensions are small, argues Guo. “Secondly, even if defect-free InP/InGaAs could be grown for a FinFET structure, intrinsic carbon doping during MOCVD growth of InP will make it n-type, and this causes a high leakage current in the transistor.”
Turning to GaAs allows greater control of carbon doping. “Although carbon could not be completely avoided, because it is an intrinsic p-type dopant for GaAs, leakage due to this mechanism can be neglected,” explains Guo.
layer formed when the silicon surface is exposed to air.
After this cleaning step the wafer is loaded into an Applied Materials MOCVD reactor, and using trimethylgallium and tertiarybutylarsine precursors, a GaAs buffer layer is grown at 400 °C, before the temperature is ramped to 580 °C and the trench filled with this alloy.
Dislocation-free growth of GaAs is possible via deposition on the {111} planes of silicon
The team began with 300 mm on-axis (001) substrates, employing a standard shallow trench isolation scheme to create regions of silicon aligned along the <110> direction with a 40 nm width and a length of 10 μm. Etching these wafers in 5 percent tertramethylammonium hydroxide at 80 °C removed the silicon. Different etch rates on different crystal planes led to V-shaped groves at the bottom of the trench formed from intersecting silicon {111} facets.
Growing on these facets is highly beneficial on three counts: Nucleation of GaAs is easier on silicon (111) than silicon (100); the glide plane of lattice mismatch dislocation is parallel to the two V-shaped interfaces between GaAs and silicon; and with this geometry, dislocations are trapped at sidewalls, rather than propagating to the surface.
Before GaAs is deposited into the trenches, silicon wafers are cleaned with a method developed by Advanced Materials that removes the thin oxide
According to a variety of characterization techniques, the quality of the GaAs in the trench is very high. Scanning electron microscopy images reveal that the overgrown GaAs has clear facets and a smooth surface, indicating high-quality GaAs. Meanwhile, X-ray diffraction shows that the GaAs is fully relaxed and of good crystal quality − and transmission electron microscopy reveals an absence of boundaries between grains and phase domains.
The engineers have also scrutinized the trenches with scanning spreading resistance microscopy. The resistance of the GaAs in the trench is about two orders of magnitude higher than that of the substrate, which has a p-type carrier concentration of 1014
cm-2 . So, in other
words, there is a very low concentration of electrically active silicon in GaAs, implying that if transistors were formed, current leakage through to the substrate would be minimal.
Attempts are now underway to reduce the width of the channel so that it is suitable for producing transistors at the 10 nm node.
“Success of selective III-V growth not only depends on growth parameters, but also on the quality of pre-growth patterning, thus you can imagine that it will need quite some work to obtain high quality material,” says Guo.
W<Ref.> XXXXXXXXXXXXX. Guo et. al. Appl. Phys. Lett. 105 062101 (2014)
Copyright Compound Semiconductor October 2014
www.compoundsemiconductor.net 71
Page 1 |
Page 2 |
Page 3 |
Page 4 |
Page 5 |
Page 6 |
Page 7 |
Page 8 |
Page 9 |
Page 10 |
Page 11 |
Page 12 |
Page 13 |
Page 14 |
Page 15 |
Page 16 |
Page 17 |
Page 18 |
Page 19 |
Page 20 |
Page 21 |
Page 22 |
Page 23 |
Page 24 |
Page 25 |
Page 26 |
Page 27 |
Page 28 |
Page 29 |
Page 30 |
Page 31 |
Page 32 |
Page 33 |
Page 34 |
Page 35 |
Page 36 |
Page 37 |
Page 38 |
Page 39 |
Page 40 |
Page 41 |
Page 42 |
Page 43 |
Page 44 |
Page 45 |
Page 46 |
Page 47 |
Page 48 |
Page 49 |
Page 50 |
Page 51 |
Page 52 |
Page 53 |
Page 54 |
Page 55 |
Page 56 |
Page 57 |
Page 58 |
Page 59 |
Page 60 |
Page 61 |
Page 62 |
Page 63 |
Page 64 |
Page 65 |
Page 66 |
Page 67 |
Page 68 |
Page 69 |
Page 70 |
Page 71 |
Page 72 |
Page 73 |
Page 74 |
Page 75 |
Page 76