This page contains a Flash digital edition of a book.
INDUSTRY POWER ELECTRONICS


One unwanted reaction is that of silicon with ammonia to create SiN. This resulting nitride can grow in an amorphous manner, destroying the crystal registration and with it the quality of the overlying GaN. Turning to a gallium wetting-layer is not a viable solution, because silicon is soluble in liquid gallium, so defects arise from the meltback of gallium. This doesn’t occur with aluminium, the only alternative wetting material, but in this case the growth conditions have to be carefully controlled to minimise eutectic-driven diffusion of silicon into the upper GaN layers. And if there are any imperfections in the quality of AlN, such as pinholes, GaN can make contact with silicon, leading to meltback defects or silicon diffusion into GaN.


To avoid all of these issues, our team at Translucent of Palo Alto, CA, has


pioneered the development of an engineered buffer that aids the transition between silicon and GaN, and returns full design freedom to MOCVD process engineers. Our buffer is an insulating, single-crystal rare-earth-oxide (REO), with a composition carefully chosen to be lattice-matched to the silicon on its lower surface. Meanwhile, an upper surface is engineered so that defect growth is quite dissimilar to that associated with GaN on silicon – and more like that of GaN on sapphire − thanks to the GaN lattice being more closely matched to its foundation.


Benefits of the REO are not limited to lattice matching: this layer is also chemically inert, so it provides a physical barrier to silicon diffusion. Consequently, it is not possible for gallium to come into contact with silicon. What’s more, epistructures grown with our engineered


substrates can maintain a high degree of lattice registration, because the REO is lattice-matched to the silicon substrate. Note that the top interface between GaN and the REO is chosen to have a small mismatch, because this softens the interface and provides a degree of compliance.


Benefits of the oxide Turning to an REO offers a new route to the production of epiwafers with a very low bow, which is a pre-requisite for processing in silicon lines. We can manage bow by pre-straining the wafer. Prior to MOCVD deposition of GaN, we make the wafer dome shaped. Without this, the MOCVD process would naturally result in wafers that are bowl-shaped – but thanks to the pre-straining, we are left with epiwafers that are very flat (see Figure 1, which shows a selection of wafers that have been measured, post REO growth, using a three-dimensional optical profilometer).


By adopting this approach, GaN epiwafers with an REO layer can be flat enough to be compatible with steppers used in microlithography. The requirements originate from the depth of field of the optical system in the stepper, and are defined in terms of maximum bow by SEMI. Wafers with a diameter of 100 mm, must have a bow below 40 μm, while those that are 150 mm and 200 mm across must have bows of less than 60 μm and 65 μm, respectively.


Figure 2. MOCVD bow during growth. This trace shows the curvature of two wafers on the same platen in a run. One was a bare silicon wafer and the other an REO template. In-situ monitoring of the entire process is via a LayTec EpiTT system that records the true wafer temperature, curvature, and reflectivity signals at 450 nm and 633 nm. These tools monitor the evolution of the GaN surface and the quality of the bulk GaN growth throughout the growth process. The start of the MOCVD run is at time = 0, and growth occurs up to 3800 s at which point the wafer begins to cool and tensile bowing starts. When unloaded after 6400 s, the two-dimensional electron gas on the silicon wafer has a curvature of 106/km, where as that grown on the REO template has a curvature of only 11/km. A curvature of 106/km corresponds to a bow of 133 µm, which is out of spec, where as a curvature of 11/km corresponds to a bow of only 14 µm, which is comfortably within spec for this sized wafer.


30 www.compoundsemiconductor.net October 2014 Copyright Compound Semiconductor


Improvements in device performance also result from inclusion of an REO. This oxide is an insulator, so it increases the transistor’s breakdown voltage. In addition, a common failure mechanism is addressed: devices often breakdown due to silicon diffusion, but this can’t happen when an REO is involved, because this oxide provides an impenetrable barrier to silicon atoms.


To mitigate this diffusion process when producing conventional devices, thicker GaN layers are required. This adds to production costs, and must be weighed against the expense associated with deposition of a REO layer. Note that the insulating nature of this oxide means


Page 1  |  Page 2  |  Page 3  |  Page 4  |  Page 5  |  Page 6  |  Page 7  |  Page 8  |  Page 9  |  Page 10  |  Page 11  |  Page 12  |  Page 13  |  Page 14  |  Page 15  |  Page 16  |  Page 17  |  Page 18  |  Page 19  |  Page 20  |  Page 21  |  Page 22  |  Page 23  |  Page 24  |  Page 25  |  Page 26  |  Page 27  |  Page 28  |  Page 29  |  Page 30  |  Page 31  |  Page 32  |  Page 33  |  Page 34  |  Page 35  |  Page 36  |  Page 37  |  Page 38  |  Page 39  |  Page 40  |  Page 41  |  Page 42  |  Page 43  |  Page 44  |  Page 45  |  Page 46  |  Page 47  |  Page 48  |  Page 49  |  Page 50  |  Page 51  |  Page 52  |  Page 53  |  Page 54  |  Page 55  |  Page 56  |  Page 57  |  Page 58  |  Page 59  |  Page 60  |  Page 61  |  Page 62  |  Page 63  |  Page 64  |  Page 65  |  Page 66  |  Page 67  |  Page 68  |  Page 69  |  Page 70  |  Page 71  |  Page 72  |  Page 73  |  Page 74  |  Page 75  |  Page 76