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INDUSTRY GaN DEVICES


We offer a portfolio of transistor technologies, with different gate lengths and breakdown voltages. Devices formed with our 0.15 μm and 0.25 μm processes are engineered to operate at 28 V, and have a minimum breakdown voltage of 70 V. Meanwhile, the GaN HEMTs fabricated with our 0.50 μm process are designed to operate at 50 V and have a minimum breakdown of 130 V (see Figure 2).


In our case, the interconnect and passive component architecture for the GaN MMIC processes has been leveraged from our GaAs MMIC technology, but modified primarily for higher operating voltages. Circuits are constructed with high-performance, edge-lifted ELC MIM capacitors, thin film resistors, and high-Q inductors that are commonly deployed in our GaAs technology. This creates a GaN technology that features a robust MMIC process with a 4 μm-thick air-bridge metal and 1 μm-thick global interconnect metals.


We were able to draw on our expertise as the world’s largest manufacturer of GaAs devices to re-engineer the back-side processing of GaN-on-SiC HEMTs, rather than following the approaches our competitors. Our efforts led to the development of a highly manufacturable process technology that includes: high-speed etching through SiC and then GaN-based materials; improved wafer mounting media involving specialized bonding wax and substrates; handling of by-product formation during high-speed etching and subsequent, repeatable removal of by-products; and back-side seed layer optimisation for good adhesion and conformal coverage in 100 μm deep vias with a width of less than 30 μm (see Figure 3 for a 30 μm x 60 μm oval substrate via that connects back-side metallization to the front-side source of the transistors).


Additional aspects of our processing technology include improvements in regards to demounting of a highly stressed thinned wafer; high-speed sawing with minimal chipping of an extremely hard SiC material system; optimisation of tape materials to provide environmentally-friendly, green material usage; and care to control interactions between all of these many processes.


Using this approach, we produce devices that deliver high-efficiency RF performance. By reducing source inductance and resistance, our HEMTs provide stable linear gain at low input power and have good 3dB/decade compression. When delivering a 3 GHz, continuous-wave input signal at a 50 V bias, the output power exceeds 5.5 W/mm, power-added efficiency is greater than 60 percent, and linear gain


is almost 19 dB higher than that produced with silicon LDMOS technology (see Figure 4).


Reliability of our devices has been proven through extensive reliability testing that complies with many JEDEC specifications. By working in collaboration with researchers at the University of Bristol, Centre for Device Thermography and Reliability, we have accurately determined the junction temperatures for the devices during reliability testing and under normal operating conditions. One of the JEDEC specifications is associated with a DC high-operating-lifetime-test that forms a basis for evaluating the mean-time to failure (MTTF). Testing involved four sets of samples from the 0.25 μm GaN-on-SiC process, with devices driven until they failed at temperatures ranging from 331 °C to 369 °C. Curve fitting revealed an MTTF of 1


On-wafer


measurements on WINs GaN-on- SiC wafers


Figure 4. RF performance on the 0.50 μm GaN-on-SiC process at 3GHz with Idq


=


10mA/mm and Vds


=50V for a


1.25 mm device achieving more than 5.5 W/mm under


continuous-wave conditions


Copyright Compound Semiconductor October 2014 www.compoundsemiconductor.net 57


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