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that it also reduces the thickness of GaN required to hit a particular blocking voltage. We anticipate that by preventing diffusion and aiding device robustness to high voltages, we may be able to trim the GaN thickness by at least 25 percent and also potentially remove all of the interlayers. These actions could result in a significant cost saving associated with device production.

A further benefit of our technology is that it is considerably different from other techniques for forming GaN-on- silicon, giving it an enviable position in terms of intellectual property. IP ownership is increasingly viewed as an important asset as the industry matures: Indeed the French market analyst, Yole Développement, recently produced a market report dedicated exclusively to GaN-on-silicon IP, underlining the importance of proper IP protection.

Promising results

Experimental results on epiwafers and HEMTs back up our claims of the virtues of our REO-based technology for GaN-on-silicon transistors. These efforts included a side-by-side comparison of a 100 mm silicon wafer, and our engineered, REO-based template that had been pre-strained to offset the stresses from MOCVD deposition. These wafers were placed in adjacent pockets in an MOCVD run conducted using a standard sapphire process for the production of 2 DEG HEMT structure. After growth, the epiwafer with the oxide interlayer had less than one-quarter of the curvature of the structure grown on bare silicon, and with a bow of just 14 μm, the epiwafer with the REO layer was comfortably within spec for processing in a silicon line (see Figure 2). In contrast, the GaN-on-silicon wafer was significantly out-of-spec.

By turning to AlN interlayers, it is possible to reduce the bow and manage defect propagation in GaN-on-silicon HEMTs. These AlN layers can also be used within our structures, but we plan to work to reduce and even eliminate them, because we expect the REO to take over much of this functionality (figure 2 shows how an REO layer can be used to bring a process

Figure 3. Transmission electron micrograph and composition analysis demonstrates that a rare- earth oxide layer can provide an impenetrable barrier to silicon diffusion.

that is out-of spec, to being comfortably within spec, in terms of wafer bow).

Impenetrability of the REO layer to silicon diffusion is proven with a combination of transmission electron microscopy and energy dispersive X-ray analysis of a structure with layers of GaN, AlN, and ErO on top of silicon (see Figure 3). According to the X-ray analysis, there is no trace of silicon in the GaN layer. In addition, no oxygen or erbium is found in the GaN, indicating that the REO does not act as a source of contamination.

High crystal quality of the HEMT structures formed on our engineered templates is revealed in X-ray diffraction plots, which feature relatively sharp AlGaN fringes. The widths of the X-ray peaks can determine dislocation densities in the epitaxial structure, according to the work of Detlef Hommel and co-workers from the University of Bremen.

Values of 600 arc seconds for the (002) reflection and 1400 arc seconds for the (102) reflection suggest that the dislocation density in the GaN layer

Figure 4. X-ray diffraction uncovers the components of an REO template and GaN 2DEG HEMT structure

Copyright Compound Semiconductor October 2014 31

is 2 x 1010


. In our view, this value

is perfectly respectable, and provides further validation that our template provides a good foundation for the subsequent MOCVD growth of GaN.

Another great attribute of our REO layer is that it leads to a growth mechanism that is the same as that for GaN deposited on sapphire, which is the most common substrate for GaN growth, but one that is unsuitable for electrical devices, due to its insulating properties.

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