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INDUSTRY POWER ELECTRONICS


Mapping of the surface of GaN grown on REO by atomic force microscopy reveals the presence of parallel atomic steps, indicating that two-dimensional step- flow growth occurs – just like it would on sapphire (see Figure 5).


The quality of the underlying undoped GaN was independently evaluated via Hall measurements – an n-doped GaN calibration layer doped to 1.1x1018 had a measured mobility of 250 m2


Device results


Using a modified GaN-on-sapphire MOCVD process, HEMT device layers were grown on Er2


O3 O3 -on-silicon (111)


templates. An AlN buffer layer was grown on the Er2


, followed by a thick


GaN layer, a 3 nm AlN interlayer, an 30 nm-thick barrier layer of Al0.25


Ga0.75 N and


a 1 nm GaN capping layer. Throughout the MOCVD run, laser reflectometry and emissivity corrected pyrometry monitored the growth of the nitride layers.


The finished wafers were processed using a standard interdigitated source and drain design (with no field plates) and employed all of the standard processing steps such as BCl3


/Cl2


reactive ion-etching and deposition of gold-free contacts that are common to today’s GaN-on-silicon FETs.


Typical results for the completed generic


device are given in Figure 6. The results confirmed that this new approach for making III-N power FETs on silicon using an REO buffer is a viable alternative to other methods commonly used to deposit GaN on silicon. We demonstrated that, using standard MOCVD processes, devices with perfectly reasonable performance can be made.


Indeed, these devices have a performance that is equivalent to those shown by similar devices not grown on-top of the REO. Additionally, we have


Figure 5. Atomic force microscopy reveals the characteristic step-flow morphology. The z-range is 4.2 nm and the RMS 0.51 nm (MOCVD courtesy of www.bluglass.com.au)


demonstrated complete MOCVD design freedom over the available MOCVD processes that can be used because of the chemical and physical properties of the REO layer.


/cm3 V-1


s-1.


What’s next? We can produce REO templates with diameters of 150 mm and 100 mm, and we are presently ramping-up our 200 mm REO production in our facility. Allied to these efforts, we are engaging with customers and promoting REO templates as a genuine alternative to the step-graded and superlattice approaches that are more commonly employed today.


During these conversations, we are pointing out that our REO material can take on the role of a gate dielectric on top of an MOCVD structure, thanks to its high dielectric constant of 12 to 15.


Our REO-based templates are not limited to serving the power electronics markets − they are attractive options for the production of LEDs and RF devices. One way that these REOs can aid LEDs grown on silicon is by introducing a mirror beneath the active region that stops light from being absorbed by the substrate.


This insertion of a distributed Bragg reflector, however, is not the only role that an REO can play – it can also allow the introduction of the more common orientation of silicon, silicon (100), into the LED industry. Deposition on this orientation of silicon is potentially very useful, because it enables the growth of non-polar and semi-polar GaN, which can lead to higher efficiencies at longer wavelengths, thanks to either the reduction or elimination of energy- sapping internal electric fields.


Figure 6. A photomicrograph of a typical device layout is shown for processed GaN-on-REO-on-Si FET that yields the following results: A drain current of 800 mA/mm, a channel mobility of 920 cm2 a channel sheet carrier concentration of 1.36×1013 /cm2 and sheet resistivity = 496 Ω/sq. (Device processing: Rick Brown, www.CayugaMicroDevices.com)


V-1 s-1 ,


This opportunity for REO-based templates, alongside their tremendous promise in power electronics, shows that there are multiple benefits to inserting an oxide layer between silicon and GaN. We hope that many will look to pursue this route, and allow us to play a significant role in helping this industry to make better compound semiconductor devices.


32 www.compoundsemiconductor.net October 2014 Copyright Compound Semiconductor


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