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INDUSTRY GaN DEVICES


Figure 2. DC performance on the 0.50 μm GaN-on-SiC process. The Ids


-Vds curve


records operation to 60 V for the nominal


160 V breakdown voltage process. The plot


reveals good sub-threshold characteristics and high Ion Ioff


/


ratio for a compound semiconductor technology


with large edge exclusion zones. All of these are induced in part by the large lattice mismatch between GaN and silicon.


As well as these material issues, there are drawbacks in device design with GaN-on-silicon. Most high performance GaN RF power amplifiers require low resistance and low inductance source vias. Backside via formation can be challenging once the silicon substrate is thinned due to excessive warpage. The thermal conductivity of silicon is inferior to that of SiC resulting in electro-thermal performance issues for


GaN-on-silicon devices that limit the power density of the transistors.


Power switching devices are less affected by this, because they generate far less heat under normal operating conditions than their RF counterparts. What’s more, power devices don’t tend to include backside source vias, simplifying backside wafer processing and reducing cost. Consequently, GaN-on-silicon technology is predominantly used in the power switch market, where it gives little away in performance to GaN-on-SiC, but is cheaper. In contrast, in the RF market there is a premium placed on performance and reliability, so GaN-on-SiC reigns supreme. Note, however, that there are niche opportunities for GaN-on-SiC for power switches, with the greatest chance of success in applications requiring blocking voltages in excess of 600 V.


Device manufacture We sub-divide the engineering of our transistor into five main areas: epitaxial design on SiC substrates, dielectric engineering, metallurgical engineering, electro-thermal design, and interface engineering. Many groups around the world have investigated these topics in detail, leading to a vast body of published literature on every one of these subjects. Insights are offered in the form of patents and papers, and we undertook a painstaking analysis to manoeuvre around existing IP.


Figure 3. Scanning electron microscopy cross-section of a transistor with an integrated source backside for low-source inductance and resistance connections. A 30 μm x 60 μm oval substrate via connects backside metallization to the front-side source of the transistors. The T-gate is visible adjacent to the source pads on the bottom of the figure. Note that the divot inside the substrate via is potting material used to prepare the sample before SEM imaging


High-voltage handling and high output power of the transistors is possible through the use of a damascene T-gate and an overlying source-coupled field plate. Minimal charge trapping and dispersive effects result from interface and dielectric engineering, enabling good, stable and repeatable device performance.


56 www.compoundsemiconductor.net October 2014 Copyright Compound Semiconductor


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