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INDUSTRY VCSELs


VCSEL). Thanks to surface emission, the VCSEL can be tested on wafer, which delivers an enormous cut in manufacturing cost and lends itself to the fabrication of laser arrays comprising multiple emitters on a single chip. By using direct butt-coupling, adding a lens to the emitting surface of the VCSEL, or by using a fibre with a built-in lens tip, it is possible to couple the emitted light into a standard multiple-mode optical fibre. In high optical output power or illumination applications, arrays of VCSELs may be used in concert with a microlens array to collimate the emitted light.


The speeds (data bit rates) of commercially available optical fibre links are held back by the light source, and presently show maximum bit rates of between 10 Gbit/s and 28 Gbit/s. The maximum operating bit rate of a VCSEL depends on several intrinsic device parameters including the damping of the modulation response, thermal effects, and aspects of device design that determine parasitic resistance and capacitance.


Figure 1. Lane rates are increasing to help to try and meet the insatiable demand for more data, and they could eclipse to 100 Gbit/s by the end of the decade.


One downside of this architecture is that it must involve the fabrication of discrete devices, with manufacturing and testing only performed on fully processed edge-emitting devices. An additional weakness is that the output from these devices shows an elliptical beam profile, which is tricky and expensive to collimate and to focus into the end of an optical fibre.


Due to these limitations, the vertical-cavity-surface-emitting laser (VCSEL) is a far more attractive class of laser diode for deployment in short-reach optical interconnects for datacentres, server farms, and supercomputers. This class of laser contains an active layer confined by two distributed Bragg reflectors (DBRs), which are formed via the growth of multiple thin epitaxial layers on a semiconductor substrate. With this device geometry, light exits the chip through either the upper or lower DBR reflector, thus in a direction that is vertical (perpendicular) to the surface of the VCSEL (see Figure 2 for top-emitting


Turbo-charging the VCSEL To spur the VCSEL to higher speeds, our team of researchers at the Technical University of Berlin (TU Berlin), Germany, at Chalmers University of Technology, Sweden, and at the UK- based epitaxial-wafer manufacturer IQE plc, has developed new device architectures that can increase data transmission speeds. This work first evolved as part of a European Commission-funded programme called VISIT – Vertically Integrated Systems for Information Transfer, during the years 2008-2011 .


We have made essential refinements to the VCSEL design (Figure 3), including replacement of the GaAs-based active layer with a strained InGaAs/AlGaAs quantum well structure to provide higher differential gain, and the introduction of separate confinement heterostructures to speed up the transport of carriers and ensure low gain compression. In addition, we trimmed the cavity length to boost optical confinement; cut the number of mirror pairs in the top distributed Bragg reflector, in order to cut reflectivity and ultimately shorten the photon lifetime; and introduced more advanced interface grading and modulation doping schemes in the DBR mirrors,


Figure 2. A typical GaAs-based VCSEL structure features an active region sandwiched between two multilayer mirrors (DBRs). Carriers are injected through the contacts on the top and bottom of the structure, with light emitting through the top. The beam profile is governed by the width of the oxide aperture.


36 www.compoundsemiconductor.net October 2014 Copyright Compound Semiconductor


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