microelectronics technology
high leakage currents in its 45 nm node Core 2 Duo process.
Advances like this, along with the introduction of metal gates, provide a massive boost to everyone developing alternative forms of CMOS, such as those who dream about replacing the conventional silicon channel with much higher mobility materials, like germanium and III-V compounds.
Although there is still much to do to make this dream a reality, some progress has been made. In particular, breakthroughs in germanium and InGaAs surface channel MOSFETs have brought the research community far closer to unleashing the potential of these high-mobility channel materials, for high drive current at scaled supply voltage.
Efforts, including those by our team of researchers at the European research center imec, have shown that germanium-based channels are very promising for making high-performance p-FETs. And similar developments, at Intel in particular, have unveiled the great potential of InGaAs channels for the n-FET.
Integrating those two strong contenders under a conventional CMOS process is formidable, and requires overcoming a handful of challenges: growth of selective and defect-free high-mobility materials on a silicon substrate, despite the intrinsic, large-lattice-mismatch; formation of ultra-low resistance contacts to a III/V material; and excellent electrical passivation of the interface between the high-k dielectric and the alternative channel materials.
I
t is nigh on impossible to overstate the progress of CMOS technology since its invention in the 1960s. Most of these tremendous gains have resulted from shrinking the size of the transistors, and for the first four decades no major modifications were needed to the design of the device that exploited the great interface between silicon and silicon dioxide.
But this pairing of silicon and its native oxide could only go so far, and more recently progress has hinged on the introduction of new materials. For example, in 2007 Intel introduced a high-k dielectric based on the far more exotic material, hafnium, into its production process to prevent
The latter challenge is particularly tough in the case of CMOS integration, because a common gate stack strategy is necessary in order to passivate the different materials for forming surface-channel devices: germanium (p-FET) and InGaAs (n-FET). We are now working on this problem, and considering a range of architectures for combining a III-V n-MOSFET and a germanium p- MOSFET, such as that shown in Figure 1.
Nearly all well-functioning high-k dielectrics that employ a low-equivalent-oxide-thickness (EOT) material on silicon
still start with a thin Si/SiO2 interfacial layer, and the high- k dielectric is then deposited on top. This route is chosen because the pairing of silicon and its native oxide is a great combination in terms of material quality. A great deal
of effort has been applied to mimicking this silicon/SiO2 interface on germanium and III/V materials by introducing an ultra-thin silicon cap that is just a few monolayers thick and can act as a surface passivation layer. Germanium channels have benefited from this approach, and we have
July 2010
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