industry interview
Figure 5. Injection
velocity at the virtual source in InGaAs and InAs HEMTs fabricated at MIT as a
function of gate length at
VDD=0.5 V. For reference, results from bulk and
strained silicon CMOS are also included
(VDD=1.1-1.3 V). In spite of operating at less than half the voltage, InAs and InGaAs HEMTs significantly outperform silicon MOSFETs
yield the required short-channel effects at the desired lengths scales, we can resort to developing three- dimensional devices. In the silicon domain, FinFETs and nanowire transistors are serious contenders for the 22 nm CMOS node and perhaps beyond. Three-dimensional device demonstrations in III-Vs give hope to this avenue. GaAs FinFETs and InAs nanowire transistors with impressive characteristics have been demonstrated at Purdue, Lund University and other places.
Dealing with the holes Most III-Vs have very high electron mobilities, making them ideal for n–channel devices. But CMOS needs p-channel transistors too, and the hole mobility for III-Vs is too low - for many arsenides, it is actually lower than it is for silicon. Mobilities in silicon have improved through the addition of strain in the material, with the performance of the p- channel now approaching that of its n-type cousin. It will be interesting to see if the same trick will work for the arsenides.
Other options for the p-channel are also available. Measurements have revealed antimonides mobilities in the 1500 cm2/V.s range and p-channel transistors have already been fabricated. Germanium transistors are also
Acknowledgements Research on III-V logic technology at MIT has been sponsored in the last few years by the FCRP Focus Center on Material, Structures and Devices (MSD) and Intel Corporation.
Further reading S. Oktyabrsky and P. D. Ye (Editors), “Fundamentals of III-V Semiconductor MOSFETs”, Springer 2010. M. Heyns and W. Tsai (Guest Editors), MRS Bulletin, Special Issue on “Ultimate Scaling of CMOS Logic Devices with Ge and III-V Materials”, Vol. 34, No. 7, July 2009. M. Radosavljevic et al., “Advanced High-K Gate Dielectric for
22
www.compoundsemiconductor.net July 2010
Figure 6. This diagram outlines key challenges to a manufacturable III-V CMOS logic technology
of interest. Germanium has a high hole mobility that is enhanced through strain. It also has the advantage of being nearly lattice-matched to GaAs. This suggests a possible CMOS platform in which germanium and III-V transistors are integrated side by side.
Last but by no means least on the list of major challenges is the need for a future III-V CMOS technology to closely “look and feel” like the silicon incumbent. Meet this goal and III-V CMOS can then exploit the tremendous economy of scale in the silicon industry. The most likely incorporation of III-Vs in the CMOS road map is via an enhancement to the existing technology through the insertion of a III-V channel - much like the recent additions of high-K/metal gates or strain. Exactly how this plays out will be influenced by what emerges as the best option for the p-channel device, and it is possible that the future will witness two different channel materials sitting side by side, on top of a silicon wafer.
With III-Vs knocking on the door of the CMOS roadmap, it’s clear that the present generation of III-V scientists and engineers have an opportunity ahead of them to shape the future of mainstream electronics. Has there ever been a better time to be a III-V semiconductor technologist?
High-Performance Short-Channel In0.7Ga0.3As Quantum
Well Field Effect Transistors on Silicon Substrate for Low Power Logic Applications.” 2009 IEEE International Electron Devices Meeting, p. 319. D.-H. Kim, J. A. del Alamo, D. A. Antoniadis, and B. Brar, “Extraction of Virtual-Source Injection Velocity in sub-100 nm III-V HFETs.” 2009 IEEE International Electron Devices Meeting, p. 861. D.-H. Kim and J. A. del Alamo, “30 nm E-mode InAs PHEMTs for THz and Future Logic Applications.” 2008 IEEE International Electron Devices Meeting, p. 719.
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