industry interview
they are the only materials other than silicon with a well- established manufacturing and reliability record.
Figure 2. Transmission electron microscopy reveals a gate length for the HEMT of 30 nm
Room on the roadmap? The bad news for the III-Vs is that there is a huge barrier for insertion of any new channel material into the CMOS roadmap. At the earliest insertion point that seems plausible today, the gate length will be at most in the 10- 15 nm range. This means that the entire transistor will fit in a footprint of less than 100 nm, making it small enough to integrate tens of billions of devices on a single chip. If a disruptive technology such as III-Vs is to stand any chance of success, it will also need to substantially outperform the best scaled silicon option of that day – a performance gain of 30-50 percent seems to be the minimum.
On top of this, a III-V-based approach must also offer the promise of a few scaled generations beyond the insertion node, plus cost-effective manufacturing and unprecedented levels of reliability. Do III-Vs have any chance of success?
One way to answer this question begins by seeing what we can learn from today’s devices. An excellent model system is the HEMT, a device with near terahertz capabilities that we have been investigating at MIT for the last few years. Our effort has focused on studying the logic characteristics of InGaAs and InAs HEMTs with gate lengths down to 30 nm. The encouraging news is that these devices exhibit logic characteristics, in terms of current drive and short-channel effects, rivaling state-of- the-art silicon MOSFETs with equivalent gate lengths.
Our transistor portfolio features HEMTs with a channel just 10 nm thick that includes a pure, 5 nm-thick InAs core (see figures 1 and 2). The InAlAs barrier in this structure has an effective thickness of just 4 nm, and the combination of this thin barrier and channel creates a device with excellent short-channel effects that can be scaled to 30 nm gate lengths.Devices with this gate length have excellent output characteristics with very
good current drive. HEMTs operating in enhancement
mode (VT=80 mV), an essential requirement for logic applications, have a peak transconductance 1.8 mS/µm
at a VDS of just 0.5 V. Measuring performance at this source-drain voltage makes a lot of sense, because if III-V CMOS technology is to succeed, it will have to work at voltages substantially below 1 V.
For logic applications, subthreshold characteristics are more relevant (see Figure 3). Our measurements on 30 nm gate length devices show the drain current dropping sharply below threshold, and the subthreshold swing, which characterizes this drop off, is 73 mV/dec. In addition, the threshold voltage depends little on the value
of VDS. This is an important figure of merit in logic applications, called DIBL for drain-induced current lowering, because it insures the reliable operation of the
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www.compoundsemiconductor.net July 2010
transistors in diverse circuit environments. Our device has a DIBL of 85 mV/V. This value and that for the subthreshold swing are as good as the best silicon MOSFETs of similar gate lengths.
Though less relevant for logic applications, these devices also display remarkable high-frequency characteristics. At
a VDS of 0.5 V, they have a current gain cut-off frequency ft of 601 GHz and a power-gain cut-off frequency fmax of 609 GHz. As far as we know, this is the first transistor of any kind, on any material system, that simultaneously
exhibits both ft and fmax in excess of 600 GHz. The important implication of these results is that minimizing parasitics and enhancing short-channel effects not only optimizes logic operation - it also yields extraordinary frequency response. This bodes well for the prospects of a future ultra-low power, mixed-signal, terahertz-logic technology based on III-Vs.
One way to make a meaningful assessment of the logic potential of candidate device technologies is to define a figure of merit that integrates performance and short- channel effects. Since key goals in scaling are to maximize the “on” current and minimize the “off” current, a
suitable figure of merit is the value of ION for a fixed IOFF at a fixed operating voltage.
We have determined this figure of merit for our HEMTs, and found that it not only exceeds that for current CMOS technology – it beats that predicted for future generations of the incumbent technology too (see Figure 4). This performance gap is more impressive than it first appears, because silicon MOSFETs have a typical source resistance of 80 Ohm.µm, nearly three times lower than that of our InAs HEMTs. Clearly, there is plenty of headroom for improvements in the performance of our III-V transistors, so long as the extrinsic portion of the device can be properly engineered. One wonders, in fact, how far III-Vs could go?
It takes some work to answer this question. The first step is to extract the electron injection velocity at the virtual source, which is the velocity that matters to determine the current in a FET in saturation. We have recently measured this in great detail for different channel compositions, and obtained values in excess of 3x107 cm/s for 30-40 nm
gate-length devices operating at VDS=0.5 V (see Figure 5). This set of results shows that increasing the indium- content in the channel increases injection velocity, and that is it possible to reach values that are twice those seen in strained silicon. What’s more, this doubling of speed is possible with operating voltages that are less than half of those used in strained silicon CMOS. Any evaluation of the true potential of III-Vs must also consider potential implications of their low effective mass, such as their small density of states (DOS) and corresponding low quantum capacitance. This could blunt the scaling of the vertical dimensions of the FET and its overall scalability.
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