interview industry
Is nanometer-scale III-V CMOS cool enough to rejuvenate Moore’s Law?
Scaling silicon ICs involves packing transistors closer and closer together, and this is pushing the power density on the chip towards its limit. Switching to III-V CMOS offers a promising way forward, but can this alternative technology be scaled to a few nanometers, manufactured in really high-volume and made in such a way that it has the look and feel of the silicon incumbent? Jesús del Alamo from MIT discusses the issues.
I
n 1971 the silicon industry entered a new era: production of the first programmable computer processors. The debut chip, the Intel 4004, purred away at 740 kHz and employed 2300 transistors with a line width of 10 µm.
Since then Intel has continually improved performance levels through scaling and technology innovation: its Core i3, Core i5, and dual-core mobile Core i7 processors that were released in the last year or so zip along at gigahertz speeds, and contain billions of transistors with feature sizes of tens of nanometers.
This tremendous improvement in chip performance that has occurred over the last four decades is a largely a result of scaling down the dimensions of the silicon transistor. Continuing in this vein will bring about further
progress, but it is getting much harder with every new CMOS generation. That’s because with increases in transistor density, power dissipation has reached a practical limit and chips are running very hot. There is now no headroom left unless one is willing to use expensive new packaging and active cooling.
The way forward in this new “power constrained scaling” phase of the silicon industry is to reduce the transistor’s operating voltage. With silicon transistors, driving the voltage down while simultaneously enhancing transistor performance has become increasingly difficult, and the operating voltage for CMOS has bottomed at about 1 V for the last few generations of technology. This trend is a serious threat to further progress for the silicon IC. One way to alleviate this looming bottleneck is to switch to a channel with a far higher carrier velocity, which would allow further voltage scaling and better performance.
Several materials could fulfill this role, but by far the most promising are III-V semiconductors: their capabilities at high frequencies are proven; their reliability is also well established; and their deployment in the power amplifiers of mobile phones shows they could be used to manufacture chips in high-volumes in a cost-effective manner. In fact, III-Vs seem the obvious choice, because
Figure 1. Jesús del Alamo’s group at MIT have fabricated HEMTs on an InP substrate that feature a 10 nm-thick channel, which includes a 5 nm-thick, pure InAs core surrounded by an InGaAs cladding. T he barrier is InAlAs, lattice-matched to InP. There is a low resistance InGaAs/InAlAs cap above a thin InP etch-stop layer. The gate is fabricated through a triple-recess process, and its stack includes platinum in its bottom layer, which is driven into the barrier in a thermal step. This leads to an effective reductionin the InAlAs barrier thickness to about 4 nm
July 2010
www.compoundsemiconductor.net 19
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