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The development of a reliable, manufacturable gate stack that includes a high-K gate dielectric and yields a high- quality semiconductor interface with a III-V compound semiconductor is as intriguing as any problem in modern semiconductor technology. Like all great challenges, it has been attracting great interest. Recent research from around the world has shown the great promise of ex-situ Atomic Layer Deposition (ALD) and MOCVD for depositing high-K dielectrics on suitably treated InGaAs surfaces. ALD, in particular, has demonstrated its capability to engineer the bonding structure at the III-V surface. This holds the key for Fermi level unpinning and attaining a low density of interface states.
Figure 3. The drain current of InGaAs HEMTs drops off rapidly below threshold.
To address these concerns we have recently carried out a theoretical and experimental study of gate capacitance in advanced InGaAs and InAs HEMTs. Our conclusion: there is a significant increase in the DOS effective mass and the sheet charge density in the InAs channel resulting from the non-parabolicity of its conduction band coupled with channel quantization and biaxial compressive strain. Based on these findings, we believe that it is eminently feasible to produce III-V transistors with 10 nm gate
lengths operating at VDD=0.5 V, which have a sheet carrier density in the mid 1012 cm-2 range. The upshot of these two recent results – the injection velocity and scaled gate capacitance – indicates that a 10 nm gate-length III-V FET with a thin InAs channel should be capable of reaching a drive current of about 1.5 mA/µm (this will require a source resistance of 80 Ohm.µm). If our predictions are correct, III-V CMOS can deliver a level of performance well above that of the silicon equivalent, even assuming the most optimistic scenario for the incumbent technology.
But is it possible to turn hope into reality by re- engineering our HEMTs, so that they can scale down to these dimensions and realize the desired level of performance? Probably not. Substantial gate leakage current is already present at 30 nm gate lengths (see Figure 3). This is because of the thin InAlAs barrier that separates the gate from the channel. Any further reductions in gate length will demand additional gate barrier thickness scaling yielding intolerable gate leakage currents. So, our HEMTs are already very close to their scaling limit, at least from the logic point of view. The inevitable conclusion is that a future 10 nm III-V logic FET will require a high dielectric constant (“high K”) gate dielectric, something that will only be possible via profound re-engineering of the device.
The gate stack is actually one of a handful of very challenging technical problems that must be solved before a III-V CMOS technology can become a reality (Figure 6). Scaling down transistor size is another major concern. Will it be possible to scale III-V transistors to the required dimensions, while preventing excessive short-channel effects and realizing the low levels of parasitic resistance that are required? We can’t tell at this point. Straight scaling of the extrinsic region of a modern HEMT to the dimensions required for a 10 nm III-V MOSFET would result in an external resistance two orders of magnitude too high. Addressing this is going to require extensive technology development and simulations. Fortunately, our HEMTs have also served to calibrate modern device simulators, which reproduce their characteristics quite well. These are valuable tools to predict device characteristics in the 10 nm range. If planar devices fail to
Figure 4. “On” current for an “off” current of 100
nA/µm at VDD=0.5 V as a function of gate length for InAs HEMTs made at MIT. This is a figure of merit that aggregates performance and short-channel effects. For reference, recent scaled silicon CMOS technologies are shown. These data are courtesy of D. Antoniadis (MIT) and are based on detailed analysis of Intel’s High Performance CMOS technologies presented at IEDM. Also added are projections from the International Technology Roadmap for Semiconductors
July 2010
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