Column: JESD204 standard
500MSPS, whereas Subclass 2 is for converters operating below 500MSPS. The JESD204B version also groups
devices into three different speed grades – with the source and load impedance for all three being defined as 100Ω ± 20%. The first speed grade aligns with the lane data rates from the JESD204 and JESD204A versions of the standard and defines the electrical interface for lane data rates up to 3.125Gbps. The second speed grade defines the electrical interface for lane data rates to 6.375Gbps, with the minimum differential voltage level lower at 400mV peak-to-peak than the 500mV peak- to-peak for the first speed grade. The third speed grade defines the electrical interface for lane data rates up to 12.5Gbps, with the minimum required differential voltage level defined as 360mV peak-to-peak. As lane data rates increase for the speed grades, the minimum required differential voltage level is reduced to make physical implementation easier by reducing required slew rates in the drivers.
Why is JESD204 important? In much the same way LVDS began overtaking CMOS several years ago as the technology of choice for the converter digital interface, JESD204 is poised to tread a similar path in the next few years. While CMOS technology is still available today, it has mostly been overtaken by LVDS. The speed and resolution of converters as well as the need for less power eventually renders CMOS and LVDS inadequate for converters. As the data rate increases on the CMOS outputs, the transient currents also increase, resulting in higher power consumption. While the current and thus the power consumption remain relatively flat for LVDS, the interface has an maximum speed it can support, due to the driver architecture and the numerous data lines that must be synchronised to its data clock. Figure 4 shows the different power
consumption requirements of CMOS, LVDS and CML outputs for a dual 14- bit ADC.
At approximately 150-200MSPS and
LVDS began overtaking CMOS several years ago as the technology of choice for the converter digital interface. In much the same way, JESD204 is poised to tread a similar path in the next few years
14 bits of resolution, CML output drivers consume less power than the competition. CML off ers the further advantage of requiring fewer output pairs per given resolution than LVDS and CMOS drivers, because of the serialisation of data. T e CML drivers specifi ed for the JESD204B interface have an additional advantage, since the specifi cation calls for reduced peak-to-peak voltage levels, as the sample rate increases and pushes up the output line rate. The number of pins required for the
same given converter resolution and sample rate is also considerably lower; see Table 1. There’s a synchronisation clock for each channel’s data for CMOS and LVDS outputs, and a maximum data rate of 4.0Gbps for JESD204B data transfer using CML outputs. The reasons for the progression to JESD204B using CML drivers become obvious from Table 1, which shows the dramatic reduction in pin count that can be achieved. Analog Devices has been
involved in the JESD204 standard from the start, and now off ers several converters with JESD204- and JESD204A-compatible outputs, currently developing products with outputs compatible with JESD204B.
Table 1: Pin-count comparisons for a 200MSPS ADC
14 December/January 2021
www.electronicsworld.co.uk
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