Column: JESD204 standard
the associated complexity of aligning an additional clock signal with the transmitted data at high data rates.
JESD204’s first revision As the JESD204 standard gained in popularity, it became obvious that it also needed to support multiple aligned serial lanes with multiple converters, to accommodate increased converter speeds and resolutions. This led to the first revision of the JESD204 standard, which became known as JESD204A; see Figure 2. The lane data rates remained unchanged, as did the frame clock and interface specifications. Supporting multiple aligned serial lanes allowed converters to meet the maximum supported data rate of 3.125Gbps. Although both the original JESD204
standard and the revised JESD204A were higher performance than legacy interfaces, they still lacked a key element – deterministic latency of the link’s serialised data. When dealing with a converter,
it is important to know the timing relationship between the sampled signal and its digital representation, in order to properly recreate the sampled signal in the analogue domain. This timing relationship is affected by the converter’s latency, which for an ADC is defined as the number of clock cycles between the instant of the sampling edge of the input signal and the time its digital representation shows at the converter’s
JESD204 was originally rolled out in 2006, but has undergone revisions that make it a much more attractive and efficient converter interface
outputs. Similarly, in a DAC, the latency is defined as the number of clock cycles between the time the digital signal is clocked into the DAC and the time the analogue output begins changing. In the JESD204 and JESD204A standards, there were no defined capabilities that would deterministically set the latency of the converter and its serialised digital inputs/outputs. In addition, converters were continuing to increase in both speed and resolution. These factors led to the introduction of the second revision of the standard, JESD204B.
Revision number 2: JESD204B In July 2011, the second and current revision of the standard, JESD204B, was released; see Figure 3. One of its key components was the provision for deterministic latency. In addition,
supported data rates were pushed to 12.5Gbps, broken down into different speed grades of devices. The revision also called for a transition from using the frame clock to using the device clock as main clock source. The JESD204B revision provides
a mechanism to ensure that from one power-up cycle to the next, and across link resynchronisation events, the latency is repeatable and deterministic. One way to accomplish this is by initiating the initial lane alignment sequence in the converter(s) simultaneously across all lanes at a well-defined moment by using an input signal called SYNC~. Another implementation is to use the SYSREF signal, which acts as a master timing reference, aligning all internal dividers from device clocks and local multiframe clocks in each transmitter and receiver, ensuring deterministic latency through the entire system. This is a newly-defined signal for JESD204B. There are three device subclasses in
the JESD204B specification: • Subclass 0 – no support for deterministic latency;
• Subclass 1 – deterministic latency using SYSREF; and
• Subclass 2 – deterministic latency using SYNC~. Subclass 0, in effect, is a JESD204A
link. Subclass 1 is primarily intended for converters operating at and above
Figure 3: Second (current) revision – JESD204B
Figure 4: CMOS, LVDS and CML driver power comparison
www.electronicsworld.co.uk December/January 2021 13
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