Column: JESD204 standard
The growing importance of the
JESD204 converter interface standard
By Jonathan Harris, Applications Engineer, Analog Devices
converter interface is steadily picking up steam and looks to become the protocol of choice for future converters. The JESD204 interface brings this efficiency and offers several advantages over its complementary metal oxide semiconductor (CMOS) and low voltage differential signaling (LVDS) predecessors in terms of speed, size and cost. JESD204 was originally rolled out
A
several years ago, but has undergone revisions that make it a much more attractive and efficient converter interface. The standard applies to both analogue-to-digital converters (ADCs), as well as digital-to-analogue converters (DACs), and is primarily intended as a common interface to FPGAs – but can be used with ASICs, too. Designs employing JESD204 benefit
from a faster interface to keep pace with the faster sampling rates of converters. In addition, a reduced pin-count leads to smaller package sizes and fewer trace routes that make designing boards easier and cheaper. The standard is also easily scaleable. As the standard has been adopted
by an increasing number of converter vendors and users, as well as FPGA manufacturers, it has been refined and
s the resolution and speed of converters increases, the demand for a more efficient interface grows. Now, a new
new features added that have increased efficiency and ease of implementation. Since its introduction in April 2006, the standard has seen two revisions, now standing at Revision B.
What is JESD204? The JESD204 standard describes a multi-gigabit serial data link between converter(s) and a receiver, commonly a device such as an FPGA or an ASIC. In the original, 2006 version of JESD204, the serial data link was defined for a single serial lane between a converter or multiple converters and a receiver; see Figure 1. The lane shown is the physical interface between M number of converters and the receiver, which consists of a differential pair of interconnects using current mode logic (CML) drivers and receivers. The link shown is the serialised data link established between the converter(s) and the receiver. The frame clock is routed to both, and provides the clock for the JESD204 link between the devices. Lane data rate is between 312.5Mbps
and 3.125Gbps, with both source and load impedance defined as 100Ω ± 20%. The differential voltage level is defined as nominally 800mV peak-to-peak, with a common-mode voltage range from 0.72V to 1.23V. The link uses 8b/10b encoding that incorporates an embedded clock, removing the necessity for routing an additional clock line and
Figure 1: The original JESD204 standard, introduced in 2006
Figure 2: First revision – JESD204A
12 December/January 2021
www.electronicsworld.co.uk
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