Data acquisition
before being sampled and the foldback (alias) error, which is introduced at the quantizer, also sees this filter. The signal and the alias error will see the same noise transfer function as the sigma- delta loop, and both will have similar noise shaping as the quantization noise in sigma-delta architectures. Thus, the frequency response of the CTSD loop naturally rejects input signals around integer multiples of the sampling frequency, acting as an antialiasing filter.
RESISTIVE INPUT
Figure 11. Discrete-time and continuous-time modular block schematics.
Having resistive inputs on signal and reference inputs makes it easier to drive than the sample- and-hold configurations. With constant resistive inputs, there is no kickback and the driver can be completely removed. The input is distortion free, as shown in Figure 13. And since the input resistance is constant, the retuning of the system for gain errors is also eliminated.
time of sampling. If the kickback does not settle before the next sampling, it will result in an error being sampled, thus corrupting the ADC input. Figure 10 shows the kickback on the DTSD
ADC. If, for example, the sampling frequency is 24 MHz, the data signal needs to settle within 41 ns. Since the reference is also a switched capacitor input, a high bandwidth buffer is also needed on the reference input pin. These input signal and reference buffers add to noise and drop the overall performance of the signal chain. Furthermore, the distortion components from the input signal driver (around the S&H frequency) further adds to antialiasing requirements. Also, with switched capacitor inputs, changes in the sampling speed will result in varying input current. This could result in retuning of the system for reducing gain error generated in the driver or the preceding stage while driving the ADC.
CONTINUOUS-TIME SIGMA-DELTA ADC A CTSD ADC is an alternative sigma-delta ADC architecture that takes advantage of principles such as oversampling and noise shaping, but that has an alternative means of implementing the sampling operation that delivers significant system benefits. Figure 11 shows a comparison of a DTSD architecture and CTSD architecture. As we see in the DTSD architecture, the input is sampled before the loop. The loop filter H(z) is discrete in time and implemented using switched capacitor integrators. The feedback DAC is also switched capacitor based. As there is sampling at the input, which will result in an aliasing problem
from fS, an additional antialiasing filter is required on the input before it is sampled. CTSD does not have a sampler at the input.
Rather, it is sampled at the quantizer inside the loop. The loop filter is now continuous-time using continuous-time integrators, and so is the feedback DAC. Similar to the quantization that gets shaped, the aliasing due to sampling gets shaped as well. This results in an almost nonsampling ADC, making a class of its own.
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The sampling frequency of the CTSD is fixed, unlike in the DTSD where the sampling frequency of the modulator can be easily scaled. Also, CTSD ADCs are known to be less tolerant to jitter than switched capacitor equivalents. Off-the-shelf crystal or CMOS oscillators provide low jitter clocks to ADCs locally, which helps avoid transmitting low jitter clock over isolation and reduces EMC.
Analogue inputs can be bipolar even though the ADC has unipolar supply. This can remove the need for level shifting from a bipolar front end to the ADC. The dc performance of the ADC may not be the same as the input resistor now has input common-mode dependent current as well as the input current. The reference load is also resistive, which reduces switching kickback, hence a separate reference buffer is not required. The resistor for a low-pass filter can be made on-chip so that it can track along with on-chip resistive load (as they could be of the same material), for reduced gain error temperature drift. CTSD architecture is not new, but the megatrends in industrial and instrumentation markets demand dc and ac precision performance at higher bandwidths. Moreover, customers prefer a single platform design that would cater to most of their solutions in order to reduce their time to market.
Figure 12. Frequency response of a CTSD modulator.
The two primary benefits of CTSD are the inherent alias rejection and the resistive inputs for signals and reference.
INHERENT ANTIALIASING
Moving the quantizer inside the loop results in inherent alias rejection. As shown in Figure 12, the input signal passes through the loop filter
CTSD architecture has been the choice in a broad set of applications ranging from high performance audio to cellular handset RF front end due to a number of advantages over other types of ADCs. The benefits include greater amenability to integration and low power consumption, but also, and possibly more importantly, because using a CTSD solves a number of significant system-level problems. Due to a number of technological shortcomings, the use of CTSD has previously been limited to relative audio
frequency/bandwidth and lower dynamic range. Therefore, high
performance Nyquist rate converters such as successive approximation ADCs and oversampled DTSD converters have been the mainstream solution for precision, high
performance/medium bandwidth applications. However, recent
Figure 13. Input settling for CTSD.
technology breakthroughs introduced at Analog Devices
September 2023 Instrumentation Monthly
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