Data acquisition


filter and decimation functionality. The basic oversampling modulator in sigma-delta ADCs shapes the quantization noise such that most of it occurs outside the bandwidth of interest, resulting in an increased overall dynamic range at low frequencies, as shown in Figure 4. The digital low-pass filter (LPF) then removes the quantization noise outside the bandwidth of interest, and the decimator reduces the output data rate back to the Nyquist rate.


For SAR ADCs, the gap between the input signal


BW and sampling frequency is not huge, hence we need a higher order filter that calls for a complex, higher order filter design with more power and more distortion. For example, if a 200 kSPS sampling speed SAR has an input BW of 100 kHz, the antialiasing filter will need to reject an input signal of >100 kHz to make sure there is no aliasing. This requires a very high order filter. Figure 7 shows the steep curve demand.


Figure 4. An example of oversampling.


Noise shaping is the other technique to reduce the quantization noise. In sigma-delta ADCs, a low resolution quantizer (one bit to five bits) is used inside a loop after the loop filter. A DAC is used as feedback to subtract the quantized signal from the input, as shown in Figure 5.


Figure 7. Alias requirement. Figure 5. Noise shaping.


The integrator will keep summing up the quantization error resulting in shaping of the quantization noise to higher frequencies, which then can be filtered using a digital filter. Figure 6 illustrates the power spectral density (PSD) of the output x[n] of a typical sigma-delta ADC. The noise- shaping slope depends on the order of loop filter H(z) (see Figure 11) and is (20 × n) dB/decade, where n is the order of the loop filter. The sigma- delta ADC achieves a high resolution in-band by a combination of noise shaping and oversampling.


In-band bandwidth is equal to fODR/2 (ODR stands for output data rate). Higher resolution can be obtained by increasing the order of the loop filter or by increasing the oversampling ratio.


If a sampling speed of 400 kSPS is chosen to relax the order of the filter, the rejection is needed for >300 kHz input frequency. Increasing the sampling speed will increase the power, and for double speed, the power would also be doubled. Further oversampling at the cost of power will further relax the antialiasing filter requirement, as the sampling frequency is much higher than the input BW. In sigma-delta ADCs, input is oversampled at a much higher OSR, so the antialiasing filter requirement is relaxed as the sampling frequency is much higher than the input BW, as shown in Figure 8.


Figure 9. AA filter requirement for various architectures.


the number of passive components. To get better phase matching in multichannel applications, all the components in the signal chain must match well. As a result, components with tighter tolerance are required.


Figure 8. Antialiasing filter requirement in sigma-delta.


Figure 9 gives an idea of the AAF complexity for SAR and discrete-time sigma-delta (DTSD) architectures. If we take a –3 dB input bandwidth of 100 kHz to achieve 102 dB attenuation at


sampling frequency fS, a third-order antialiasing filter will be needed for a DTSD ADC while getting


the same attenuation at fS will require a fifth-order filter using a SAR ADC. For a continuous-time


sigma-delta (CTSD) ADC, the attenuation is inherent, so we do not need any antialiasing filter.


Figure 6. Oversampling and noise shaping plot.


ALIASING To combat aliasing in high performance applications, higher order antialiasing filters are used to avoid any amount of foldback. An antialiasing filter is a low-pass filter that band limits the input signal and ensures that there is no frequency component in signal beyond the bandwidth of interest that can fold back. The filter performance will depend on how close the out-of-


band signal is to fS/2, and the amount of attenuation required.


Instrumentation Monthly September 2023


These filters can be a pain point for system designers, and they have to optimise them for the droop they provide in the band of interest and provide as much rejection as possible. They also add a lot of other errors like offset, gain, phase error, and noise to the system, thus reducing its performance.


Also, high performance ADCs are differential in nature, so we need twice


Figure 10. Sampling kickback.


Continued on page 30... 29


SWITCHED CAPACITOR INPUT Switched capacitor input sampling relies on the settling time of sampled input onto a capacitor, creating a demand for charging/discharging transient current when the sampling switch is turned on/off. This is called kickback on the input and calls for an input driving amplifier that can support these transient currents. Also, the input is required to be settled at the end of the sampling time and the accuracy of the input sampled determines the performance of the ADC, implying that the driving amplifier needs to settle quickly after the kickback event. This leads to the need for a high bandwidth driver that can support fast settling and absorb the kickback of the switched capacitor operation. In switched capacitor inputs, whenever the sampling is ON, the driver immediately has to supply the charge for the hold capacitor. This sudden surge in current can only be provided in time if the driver has sufficient bandwidth capabilities. Due to the parasitics of the switch, there will be kickback on the driver at the


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