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September, 2018


www.us-tech.com


Verifying Twisted Pair Relationships with a Continuity Tester


Continued from page 65


made before those of pairing and capacitance. When a conductor re - sistance exceeds the current resist- ance threshold, pairing and capaci- tance measurement will not be made on that conductor and the cable will fail for reason of excessive resistance. When resistances are acceptable, the tester automatically moves on to check pairing and capacitance. The conductor order detailed


here applies to straight-through Ethernet cable. For crossover Ether - net cable, the conductor order will be different, but the pairing will be the same as viewed from one side of the cable.


When there is a mix of wire


types within a cable, i.e. when only some are twisted pairs, prior to test- ing, the pairs can be defined in the match data only for those wires that are twisted.


Multiconductor continuity tes -


ters can test twisted pair cables to check for correct twisted pair rela- tionships. A pass indication will


Boundary Scan —When Does Using It Make the Most Sense?


Continued from page 64


nents need to be connected on a scan chain, but that scan chain must be designed with good signal integrity practices to ensure reliability. As with all well-designed PCBs, a power and ground layer should be utilized to help signal integrity and reduce EMI. If possible, every JTAG signal should be paired with a ground con- nection. If performing boundary scan


test through a fixture and making connections with pogo pins, multiple ground connections should be used, and each ground contact point should be placed as close to the signal con- tact point as possible. Finally, each JTAG signal should be terminated to minimize reflections and ensure a working and reliable scan chain. Each person that needs access


to a JTAG port may have different requirements in terms of component access and speed. Circuit designers need to be aware of each set of requirements and that those require- ments can be met by configuring the JTAG port as needed. For example, it may be benefi-


cial to place a microprocessor on a scan chain separate from other, slow- er JTAG devices to enable high-speed JTAG communication with that processor. By following good DFT practices, companies can ensure suc- cessful, reliable, and fast boundary scan test at all phases of the product lifecycle.


Contact: Corelis, Inc., 13100


Alondra Boulevard, Suite 102, Cerritos, CA 90703 % 562-926-6727 fax: 562-404-6196 E-mail: ryan.jones@corelis.com Web: www.corelis.com r


Twisted pair cable with two wiring errors. This defect will pass a continuity test and must be discovered through capacitance measurement.


show that the wire resistances are correct and that the wires are paired well. If a target capacitance value and tolerance has been specified, then the values shown in the test data are within the capacitance tol- erance.


This method can also be used to


verify spool-to-spool consistency of wire twist quality. Contact: CAMI Research, Inc.,


42 Nagog Park, Suite 115, Acton, MA 01720 % 978-266-2655 fax: 978-266-2658 E-mail: info@camiresearch.com Web: www.camiresearch.com r


Page 67


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