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September, 2018


When Does Using Boundary Scan Make the Most Sense?


By Ryan Jones, Senior Technical Marketing Engineer, Corelis, Inc. T


he term “boundary scan” often has different meanings depend- ing on who is using it. For


hardware design and test engineers, boundary scan refers to a widely practiced test standard, also known as JTAG IEEE-1149.1, which can reduce costs, speed up development and improve product quality for elec- tronics manufacturers around the world. Boundary scan solutions are beneficial across multiple industries and can meet a wide variety of test requirements. Boundary scan applications


require the addition of IEEE-1149.1 architecture to components. This architecture is comprised of bound- ary scan cells attached to each signal pin on a component. These cells can force data to, and capture data from, external pins or internal core logic signals. Test data is serially shifted into the boundary-scan cells and cap- tured data is serially shifted out by a serial data path, called the scan path or scan chain, and then externally compared against expected results. Boundary scan presents oppor-


tunities to extend test coverage and in-system programming (ISP), with- in and between components populat- ed on PCBs. But, when does using boundary scan tools make the most sense?


Lack of Physical Access In many cases, the decision is


an easy one because other test meth- ods cannot accommodate the size of the products. As PCBs have gotten smaller, boundary scan tools are often the only viable choice for test- ing and debugging, due to a lack of space to attach traditional test fix- tures on the products. This is especially true of PCBs


with BGA component packages, where interconnects are not accessi- ble with external probes and other test methods are extremely costly. Access is further limited by increased circuit density and the use of fine- pitch components. Boundary scan test solutions take advantage of capabilities built


into the components, using only four signals (plus one optional asynchro- nous reset) to control component pins, regardless of package, form fac- tor and probe accessibility. A single, small connector or a set of test points on a PCB can provide electronic access to test capabilities for open, short and bridging faults, as well as


boundary scan systems are compared with expensive and bulky test equip- ment, such as bed-of-nails systems and flying probes. Many industries have seen a


manufacturing shift from low-mix, high-volume to high-mix, low-vol- ume. When companies are creating multiple products that require test-


software packages that integrate with large scale military and aero- space test stations. One of the principal benefits of


having a JTAG port on a board is that it is always there, regardless of where the product is in its lifecycle. New developments and applications of IEEE-1149.1 and related stan- dards have enabled the use of JTAG in many other product lifecycle phases.


Hardware engineers can use it


to help debug prototypes, software engineers can use it to gain confi- dence in the hardware, allowing them to focus on software issues or to load and execute code on an embed- ded system. Manufacturing and pro- duction can use it for acceptance test- ing, and field service engineers can use it for in-system programming capabilities to perform firmware upgrades in the field. Design and test applications


Boundary scan uses only four signals to check for opens, shorts and bridging.


embedded functional test capabilities within the components. The increased signal speed of


today’s PCBs has brought on new failure modes, such as timing related defects, driving new areas of concern for test. These issues can be tested and diagnosed by utilizing a micro- processor’s JTAG port to execute tests at full speed, allowing defects to be discovered early in the prototype and production processes. JTAG-con- nected processor cores enable at- speed testing of high-speed memory, transceivers, and many other inter- faces utilized by embedded systems.


High-Mix Manufacturing Accessibility and decreased


product size are not the only reasons companies choose boundary scan over more traditional testing meth- ods. Manufacturing processing and cost savings can also be key factors, especially when portable, desktop


ing, boundary scan solutions can be used in an agile manner to test a wide variety of products with mini- mal shop floor footprint. By selecting boundary scan as a testing method, the cost of developing testing fixtures for each individual product is elimi- nated. By utilizing IEEE 1149.1,


Corelis tools are designed to deploy boundary scan solutions at any scale, quickly, easily and inexpensively. This method has a lower start-up cost than most other structural and functional testing methods, including bed-of-nails, automated optical inspection, and fixtureless in-circuit flying probe testing. Companies can begin boundary


scan testing with only a PC-connect- ed benchtop system. Corelis covers a wide range of boundary scan solu- tions to fit many applications. Systems range from simple start-up systems to extensive hardware and


that utilize the JTAG port include: PCB manufacturing test; program- ming devices, such as flash, SEEP- ROM, FPGA, and CPLD; circuit board bring-up and debug; compo- nent/device verification; reduction of test points for bed-of-nails test access; and processor debug, emula- tion and functional test.


Design for Test While a JTAG port can provide


many conveniences throughout a product’s lifecycle, it is important to understand that there is a hardware design element involved in which the JTAG devices must be properly con- nected to one another and accessible by a JTAG controller. A circuit board design for test (DFT) analysis is an integral part of the design process to allow access to the JTAG port. Without a functional scan chain


connecting the JTAG devices, PCBs will not be testable using boundary scan testing methodologies, leading to reduced test, diagnostic, and in- system programming capabilities. Not only do all JTAG compo-


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