March 2026
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be implemented quickly and easi- ly. Test effort and costs are there- fore extremely low for the contract manufacturer, as they only need to provide the equipment.
Hardware Conventional test systems
are large and expensive, due to needle bed adapters or functional test systems. However, it does not take much to test at a similarly high level as production at the en- gineer’s workstation. Only an em- bedded JTAG solutions controller such as the SCANFLEX II CUBE saves space and acquisition costs and forms the basis for extensive test scenarios. Developers can generate
tests themselves, enabling them to hand over a functioning prod- uct to production, including the test program. The tools included in the embedded JTAG solutions software also simplify the work enormously. A test coverage ana- lyzer provides information about which pins are sufficiently tested and which are insufficiently test- ed. This allows open problem ar- eas or possible time and space savings (e.g. due to superfluous test points) to be identified.
Low Effort The effort required for the
initial tests is low, and the devel- oper does not need much to gen- erate the tests. First and fore- most, information is required that the developer should be very familiar with: which compo- nents of which type are on the board, and how the individual pins of the components are con- nected to each other. The component types only
need to be assigned to the corre- sponding models. For example, there is a model for each bound- ary scan-capable component that describes the boundary scan structure of the IC (the so-called BSDL (Boundary Scan Descrip - tion Language) model). Depen - ding on the supplier, there are also various models for describ- ing non-boundary-scan-capable components (e.g., RAM compo- nents or driver ICs). The models are provided by
the test solution, and the re- quired CAD data is limited to a net and component list. These can be obtained from the circuit diagram, which is usually al- ready available in the early stages of PCBA development. The advantage: Problems that may arise during test generation can be easily resolved, or a de- sign that is unfavorable for test depth can be changed quickly and easily. The generated tests are then already available for the first prototype. This can be tested with ex-
actly the same quality as the pi- lot series and ultimately the se-
TR7600FB SII High Clarity 3D AXI
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ries product: same test depth, same pin-accurate error state- ment. Since the test bus required for boundary scan has already been designed to be adaptable on the device under test (e.g., via a connector), this interface can also be used to load the FPGAs or CPLDs or to store the boot- loader in the program flash. The resulting savings are obvious. Thinking about testing dur-
one and the same interface. Devel opment times are saved and time-to-market is reduced. Embedded JTAG Solutions offer the optimal interface between de-
Page 51
Why Electronics Developers Should Think About Testing... Continued from previous page
velopment and production. With a flexible controller such as the SCANFLEX II CUBE, there is a hardware platform that is also equipped for all other eventuali- ties. For example, function-based technologies for testing, program- ming, and emulation of FPGAs and processors can be easily inte- grated and later transferred in a production-ready state. Contact: GOEPEL electron-
ing development offers numerous advantages. Prototypes can be tested without firmware — and in series quality. In-system pro- gramming and testing run via
SCANFLEX II CUBE in use.
ics, LLC, 15431 Fitzhugh Road, Suite 209, Dripping Springs, TX 78620 % 512-782-2500 E-mail:
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