TECHNOLOGY MICROELECTRONICS
Again, the fabrication of optical devices is precluded at the outset. That’s because in this case the multiple layer requirements of a laser structure are too complex for a donor substrate.
There are also concerns relating to acceptable yields and costs. These arise due to the fundamentally different chemical natures of InGaAs and SiGe, which cause the etching sequences and thermal cycles for the two materials to be inherently incompatible.
Figure 1. A range of devices, including the detector shown here that is formed from a HFET structure, can be fabricated with POET technology.
Building on GaAs Against this backdrop, POET Technologies of Toronto, ON, and Storrs, CT, is pioneering a new approach that leads to superior ICs: Planar OptoElectronic Technology (POET). This revolutionary CMOS-friendly process IP, which enables p-channel and n-channel devices to be integrated monolithically in a III/V semiconductor environment, has the potential to fully replace all silicon-based CMOS circuitry.
cuts power. To equip circuits with these new materials, the mainstream silicon industry is developing technologies to add InGaAs and SiGe channels to boost electron and hole mobility, respectively.
One option pioneered independently by imec and IBM involves the growth of InGaAs in narrow trenches etched in the silicon substrate. Although there is a high lattice mismatch, the vast majority of the dislocations that form are trapped on the sidewalls at the III-V-silicon interface. This means that there is the potential for acceptable densities at the top of the trench. However, because these trenches are very small, there can be high leakage paths along the walls between the source and the drain.
What’s more, there is a very limited opportunity to vary the thickness and composition of the III-V layers that can be incorporated in the trenches, while their small size is impractical for making a laser. So it is not possible to combine high- performance InGaAs FET channels with high-performance optical emitters.
One further drawback of this approach is that the deposition of SiGe for the n-type channel requires a separate crystal growth step. Having to make two concatenated growth steps, using a rather complex process, does not bode well for acceptable yields.
An alternative approach that has been pioneered by IBM begins with the growth of III-V layers on a donor substrate. Bonding to an oxide layer transfers these high-mobility layers to a target silicon substrate. When the III-V layer is subsequently released from the donor wafer, a III-V-on-insulator structure is created on silicon. To enable the formation of p-type transistors, engineers grow an 8 nm-thick layer of SiGe on 25 nm of oxide prior to the bonding step.
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www.compoundsemiconductor.net June 2014
By turning to strained InGaAs quantum wells with indium channels of 70 percent or more, mobility and channel velocity increase, and operation of the circuit at 0.3 V should enable a ten-fold gain in performance at 80 percent lower power compared to a silicon CMOS IC.
Development of this technology started in the early 1990s in the labs of the University of Connecticut. Since then more than 18 years has been devoted to developing and proving out numerous components of the POET platform. In 2001 we formed the start-up, and we currently have 34 patents, plus another 7 pending.
Our business model is to license the III/V semiconductor process technology IP to customers and foundry partners to enable designs and produce devices that include analog,
Figure 2. Injecting charges leads to a shift in the absorption edge.
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