TECHNOLOGY MICROELECTRONICS
An example of the pioneering efforts made by this industry has been the development of a new breed of transistor with a fin protruding out of the device. This move to a three-dimensional structure, which made its commercial debut below the 28 nm node, increases device density and cut leakage. However, these advantages come at the expense of a lower yield, and the economics is challenging for fabless companies.
In addition to these economic issues, which stem from skyrocketing tapeout and wafer costs, performance gains are diminishing with every new node introduced below 28 nm. Performance figures indicate that the core voltage has saturated at 0.75-0.80 V, preventing power reductions associated with switching between on and off states, although it has been possible to trim leakage losses.
Optical CMOS
THE END IS IN SIGHT for the scaling of silicon CMOS. From the 1990s until the first few years of this millennia, simply shrinking the dimensions of silicon transistors − the only viable digital technology of the time − wrought improvements in performance that were big enough to keep pace with Moore’s Law. But since 2005, the law of diminishing returns has been more relevant: Although each additional shrink has increased performance, this has been minimal, while power increases have been significant. To blame are the parasitic resistances, capacitances and inductances that have failed to scale with reductions in device dimensions. Consequently, the power per chip is constantly pushing against the acceptable limit, while the clock rate in digital systems has stalled.
To relieve these constraints, the companies that are making processors and systems-on-a-chip have pursued different paths to superior performance. They have become more creative in managing circuit performance, while adding cores, innovating with on-chip interconnect approaches and employing better cache management. In addition, they have marketed their products in new ways, switching from traditional performance metrics such as the raw core frequencies of the processor, to alternative benchmarks that showcase their efforts in a better light.
On top of this, there has been innovation by the chipmakers. Although they are not keeping pace with Moore’s Law, the economics of moving to each new, smaller node can be justified, and power consumption has been kept in check by trimming the transistor’s operating voltage.
Another avenue being pursued by the silicon industry is to introduce optical capabilities onto the silicon IC. To do this in an economically viable manner, shrinking the dimensions of the transistors on the CMOS chip must go hand-in-hand with the introduction of a technology for connecting fibre to this device. The way forward that has attracted the most interest is that of silicon photonics: a low-loss silica waveguide connects modulators and detectors on a silicon platform. With this approach, there is the potential for CMOS drivers to co-exist on the platform.
In the past 10 years, IBM, the US government, VCs and others have spent between them more than $2 billion trying to fulfil this vision of creating optics within the CMOS IC. But even with this high level of investment − and several start-ups later – uniting photonics and electronics on a single chip is only a dream. Lack of progress has led to a consensus among the suppliers of optics, and the chips that drive them, that the economics dictates optics and logic in different processes − each optimized for their own function.
Despite this setback, the silicon industry is continuing its quest for a technology that will enable optical functions on the chip. This will have to be an alternative to CMOS technology, but one that is as similar to it as possible. Such a technology will prove essential as data rates migrate to 40 Gbit/s, 100 Gbit/s and then 400 Gbit/s, speeds that make the cost of packaging unmanageable. An additional requirement is that the IC will have to incorporate optical emitters and detectors. Attempts to develop such a platform that enables this transition from CMOS to optics are on-going, since no-one has yet to claim success.
Cutting power, boosting speed To address the power and speed limitations associated with silicon CMOS, higher mobility materials must be introduced for the n and p channels. Electrons and holes can then zip through the channel faster if the voltage is maintained, or travel at speeds similar to those associated with silicon while being driven at a lower voltage – this latter mode of operation
June 2014
www.compoundsemiconductor.net 53
Page 1 |
Page 2 |
Page 3 |
Page 4 |
Page 5 |
Page 6 |
Page 7 |
Page 8 |
Page 9 |
Page 10 |
Page 11 |
Page 12 |
Page 13 |
Page 14 |
Page 15 |
Page 16 |
Page 17 |
Page 18 |
Page 19 |
Page 20 |
Page 21 |
Page 22 |
Page 23 |
Page 24 |
Page 25 |
Page 26 |
Page 27 |
Page 28 |
Page 29 |
Page 30 |
Page 31 |
Page 32 |
Page 33 |
Page 34 |
Page 35 |
Page 36 |
Page 37 |
Page 38 |
Page 39 |
Page 40 |
Page 41 |
Page 42 |
Page 43 |
Page 44 |
Page 45 |
Page 46 |
Page 47 |
Page 48 |
Page 49 |
Page 50 |
Page 51 |
Page 52 |
Page 53 |
Page 54 |
Page 55 |
Page 56 |
Page 57 |
Page 58 |
Page 59 |
Page 60 |
Page 61 |
Page 62 |
Page 63 |
Page 64 |
Page 65 |
Page 66 |
Page 67 |
Page 68 |
Page 69 |
Page 70 |
Page 71 |
Page 72 |
Page 73 |
Page 74 |
Page 75 |
Page 76 |
Page 77 |
Page 78 |
Page 79 |
Page 80 |
Page 81 |
Page 82 |
Page 83 |
Page 84 |
Page 85 |
Page 86 |
Page 87 |
Page 88 |
Page 89 |
Page 90 |
Page 91 |
Page 92 |
Page 93 |
Page 94 |
Page 95 |
Page 96 |
Page 97 |
Page 98 |
Page 99 |
Page 100 |
Page 101 |
Page 102 |
Page 103 |
Page 104 |
Page 105 |
Page 106 |
Page 107 |
Page 108